[PATCH] D40416: [CodeGen] Rename functions PrintReg* to printReg*

[Francis Visoiu Mistrih via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL319168: [CodeGen] Rename functions PrintReg* to printReg* (authored by thegameg).

Changed prior to commit:
  https://reviews.llvm.org/D40416?vs=124144&id=124546#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D40416

Files:
  llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h
  llvm/trunk/lib/CodeGen/AllocationOrder.cpp
  llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/trunk/lib/CodeGen/DetectDeadLanes.cpp
  llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp
  llvm/trunk/lib/CodeGen/GlobalISel/Localizer.cpp
  llvm/trunk/lib/CodeGen/GlobalISel/RegBankSelect.cpp
  llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
  llvm/trunk/lib/CodeGen/InlineSpiller.cpp
  llvm/trunk/lib/CodeGen/LiveDebugValues.cpp
  llvm/trunk/lib/CodeGen/LiveInterval.cpp
  llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
  llvm/trunk/lib/CodeGen/LiveIntervalUnion.cpp
  llvm/trunk/lib/CodeGen/LivePhysRegs.cpp
  llvm/trunk/lib/CodeGen/LiveRangeCalc.cpp
  llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp
  llvm/trunk/lib/CodeGen/LiveRegMatrix.cpp
  llvm/trunk/lib/CodeGen/MIRPrinter.cpp
  llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp
  llvm/trunk/lib/CodeGen/MachineFunction.cpp
  llvm/trunk/lib/CodeGen/MachineInstr.cpp
  llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp
  llvm/trunk/lib/CodeGen/MachineScheduler.cpp
  llvm/trunk/lib/CodeGen/MachineTraceMetrics.cpp
  llvm/trunk/lib/CodeGen/MachineVerifier.cpp
  llvm/trunk/lib/CodeGen/PHIElimination.cpp
  llvm/trunk/lib/CodeGen/RegAllocFast.cpp
  llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
  llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp
  llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp
  llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
  llvm/trunk/lib/CodeGen/RegisterPressure.cpp
  llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
  llvm/trunk/lib/CodeGen/RenameIndependentSubregs.cpp
  llvm/trunk/lib/CodeGen/ScheduleDAG.cpp
  llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  llvm/trunk/lib/CodeGen/SplitKit.cpp
  llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp
  llvm/trunk/lib/CodeGen/VirtRegMap.cpp
  llvm/trunk/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
  llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
  llvm/trunk/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
  llvm/trunk/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp
  llvm/trunk/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
  llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp
  llvm/trunk/lib/Target/AMDGPU/SIMachineScheduler.cpp
  llvm/trunk/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
  llvm/trunk/lib/Target/ARC/ARCInstrInfo.cpp
  llvm/trunk/lib/Target/ARC/ARCRegisterInfo.cpp
  llvm/trunk/lib/Target/ARM/A15SDOptimizer.cpp
  llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
  llvm/trunk/lib/Target/Hexagon/BitTracker.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonBitSimplify.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonBitTracker.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonBlockRanges.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonConstExtenders.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonConstPropagation.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonExpandCondsets.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonGenInsert.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonGenPredicate.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp
  llvm/trunk/lib/Target/Hexagon/RDFLiveness.cpp
  llvm/trunk/lib/Target/Hexagon/RDFRegisters.cpp

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D40416.124546.patch
Type: text/x-patch
Size: 109769 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20171128/f87d618b/attachment-0001.bin>