[llvm] r319167 - [X86][3DNow] Add instruction itinerary and scheduling classes for femms/prefetch/prefetchw

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Tue Nov 28 04:37:35 2017
New Revision: 319167

URL: http://llvm.org/viewvc/llvm-project?rev=319167&view=rev
Log:
[X86][3DNow] Add instruction itinerary and scheduling classes for femms/prefetch/prefetchw

Modified:
    llvm/trunk/lib/Target/X86/X86Instr3DNow.td
    llvm/trunk/test/CodeGen/X86/3dnow-schedule.ll

Modified: llvm/trunk/lib/Target/X86/X86Instr3DNow.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Instr3DNow.td?rev=319167&r1=319166&r2=319167&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Instr3DNow.td (original)
+++ llvm/trunk/lib/Target/X86/X86Instr3DNow.td Tue Nov 28 04:37:35 2017
@@ -43,7 +43,7 @@ def I3DNOW_PSHUF_ITINS : OpndItins<
 }
 
 class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pat,
-             InstrItinClass itin = NoItinerary>
+             InstrItinClass itin>
       : I<o, F, outs, ins, asm, pat, itin>, TB, Requires<[Has3DNow]> {
 }
 
@@ -114,15 +114,17 @@ defm PI2FD    : I3DNow_conv_rm_int<0x0D,
 defm PMULHRW  : I3DNow_binop_rm_int<0xB7, "pmulhrw", I3DNOW_MISC_FUNC_ITINS, 1>;
 
 def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms",
-                   [(int_x86_mmx_femms)]>;
+                   [(int_x86_mmx_femms)], IIC_MMX_EMMS>;
 
+let SchedRW = [WriteLoad] in {
 def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr),
                       "prefetch\t$addr",
-                      [(prefetch addr:$addr, (i32 0), imm, (i32 1))]>;
-
+                      [(prefetch addr:$addr, (i32 0), imm, (i32 1))],
+                      IIC_SSE_PREFETCH>;
 def PREFETCHW : I<0x0D, MRM1m, (outs), (ins i8mem:$addr), "prefetchw\t$addr",
-                  [(prefetch addr:$addr, (i32 1), (i32 3), (i32 1))]>, TB,
-                Requires<[HasPrefetchW]>;
+                  [(prefetch addr:$addr, (i32 1), (i32 3), (i32 1))],
+                  IIC_SSE_PREFETCH>, TB, Requires<[HasPrefetchW]>;
+}
 
 // "3DNowA" instructions
 defm PF2IW    : I3DNow_conv_rm_int<0x1C, "pf2iw", I3DNOW_FCVT_F2I_ITINS, "a">;

Modified: llvm/trunk/test/CodeGen/X86/3dnow-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/3dnow-schedule.ll?rev=319167&r1=319166&r2=319167&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/3dnow-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/3dnow-schedule.ll Tue Nov 28 04:37:35 2017
@@ -356,6 +356,28 @@ define i64 @test_pmulhrw(x86_mmx %a0, x8
 }
 declare x86_mmx @llvm.x86.3dnow.pmulhrw(x86_mmx, x86_mmx) nounwind readnone
 
+define void @test_prefetch(i8* %a0) optsize {
+; CHECK-LABEL: test_prefetch:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    prefetch (%rdi) # sched: [5:0.50]
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    retq # sched: [1:1.00]
+  tail call void asm sideeffect "prefetch $0", "*m"(i8 *%a0) nounwind
+  ret void
+}
+
+define void @test_prefetchw(i8* %a0) optsize {
+; CHECK-LABEL: test_prefetchw:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    prefetchw (%rdi) # sched: [5:0.50]
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    retq # sched: [1:1.00]
+  tail call void asm sideeffect "prefetchw $0", "*m"(i8 *%a0) nounwind
+  ret void
+}
+
 define i64 @test_pswapd(x86_mmx* %a0) optsize {
 ; CHECK-LABEL: test_pswapd:
 ; CHECK:       # BB#0: