[PATCH] D40304: [InstCombine] PR35354: Convert load bitcast (select (Cond, &V1, &V2)) --> select(Cond, load bitcast &V1, load bitcast &V2)

[Alexey Bataev via Phabricator via llvm-commits]

ABataev added a comment.

In https://reviews.llvm.org/D40304#936480, @spatel wrote:

> This patch is building on a transform that is already suspect (see discussion starting at https://bugs.llvm.org/show_bug.cgi?id=34603#c6 ).
>
> In conjunction with the existing transform, it increases the instruction count from 3 to 5 for this example:
>
>   define i32 @store_bitcasted_load(i1 %cond, float* dereferenceable(4) %addr1, float* dereferenceable(4) %addr2) {
>     %sel = select i1 %cond, float* %addr1, float* %addr2
>     %bc1 = bitcast float* %sel to i32*
>     %ld = load i32, i32* %bc1
>     ret i32 %ld
>   }
>  
>
>
> $ ./opt -instcombine loadsel.ll -S
>
>   define i32 @store_bitcasted_load(i1 %cond, float* dereferenceable(4) %addr1, float* dereferenceable(4) %addr2) {
>     %addr1.cast = bitcast float* %addr1 to i32*
>     %addr2.cast = bitcast float* %addr2 to i32*
>     %addr1.cast.val = load i32, i32* %addr1.cast, align 4
>     %addr2.cast.val = load i32, i32* %addr2.cast, align 4
>     %ld = select i1 %cond, i32 %addr1.cast.val, i32 %addr2.cast.val
>     ret i32 %ld
>   }
>  
>
>
> Can you provide a reduced C++ source example for how we got to this IR? I couldn't repro with a simple case, so I must be missing some part of it.
>
> Also, there might be something in common with:
>  https://bugs.llvm.org/show_bug.cgi?id=35354
> or
>  https://bugs.llvm.org/show_bug.cgi?id=35284
>  ?


This patch fixes PR35354, the first one from your list. I described everything aready. We got extra bitcast from the canonicalization of load/store sequence before function inlining, but this canonialization breaks minmax pattern recognition after the inlining o а min/max functions.


https://reviews.llvm.org/D40304