[llvm] r319066 - [X86] Teach combineX86ShuffleChain that AllowIntDomain requires at least SSE2.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 27 10:15:14 PST 2017
Author: ctopper
Date: Mon Nov 27 10:15:14 2017
New Revision: 319066
URL: http://llvm.org/viewvc/llvm-project?rev=319066&view=rev
Log:
[X86] Teach combineX86ShuffleChain that AllowIntDomain requires at least SSE2.
I don't have a good test case for this at the moment. I was playing around with a change in legalizing and triggered this code to produce a PSHUFD with sse1 only.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=319066&r1=319065&r2=319066&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Nov 27 10:15:14 2017
@@ -28343,7 +28343,7 @@ static SDValue combineX86ShuffleChain(Ar
// Which shuffle domains are permitted?
// Permit domain crossing at higher combine depths.
bool AllowFloatDomain = FloatDomain || (Depth > 3);
- bool AllowIntDomain = (!FloatDomain || (Depth > 3)) &&
+ bool AllowIntDomain = (!FloatDomain || (Depth > 3)) && Subtarget.hasSSE2() &&
(!MaskVT.is256BitVector() || Subtarget.hasAVX2());
// Determine zeroable mask elements.
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