[PATCH] D40002: [RISCV] MC layer support for the jump/branch instructions of standard compress instruction set

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 updated this revision to Diff 124325.
shiva0217 added a comment.

Add test cases to check the instruction operands should not be x0.


Repository:
  rL LLVM

https://reviews.llvm.org/D40002

Files:
  lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
  lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
  lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
  lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  lib/Target/RISCV/RISCVInstrFormatsC.td
  lib/Target/RISCV/RISCVInstrInfoC.td
  test/MC/RISCV/fixups-compressed.s
  test/MC/RISCV/relocations.s
  test/MC/RISCV/rv32c-invalid.s
  test/MC/RISCV/rv32c-valid.s

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