[llvm] r318967 - [X86] Add some early DAG combines to turn v4i32 AND/OR/XOR into FAND/FOR/FXOR whe only SSE1 is available.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 24 23:20:21 PST 2017
Author: ctopper
Date: Fri Nov 24 23:20:21 2017
New Revision: 318967
URL: http://llvm.org/viewvc/llvm-project?rev=318967&view=rev
Log:
[X86] Add some early DAG combines to turn v4i32 AND/OR/XOR into FAND/FOR/FXOR whe only SSE1 is available.
v4i32 isn't a legal type with sse1 only and would end up getting scalarized otherwise.
This isn't completely ideal as it doesn't handle cases like v8i32 that would get split to v4i32. But it at least helps with code written using the clang intrinsic header.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll
llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
llvm/trunk/test/CodeGen/X86/sse1.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=318967&r1=318966&r2=318967&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Nov 24 23:20:21 2017
@@ -32967,6 +32967,16 @@ static SDValue combineAndMaskToShift(SDN
static SDValue combineAnd(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget &Subtarget) {
+ EVT VT = N->getValueType(0);
+
+ // If this is SSE1 only convert to FAND to avoid scalarization.
+ if (Subtarget.hasSSE1() && !Subtarget.hasSSE2() && VT == MVT::v4i32) {
+ return DAG.getBitcast(
+ MVT::v4i32, DAG.getNode(X86ISD::FAND, SDLoc(N), MVT::v4f32,
+ DAG.getBitcast(MVT::v4f32, N->getOperand(0)),
+ DAG.getBitcast(MVT::v4f32, N->getOperand(1))));
+ }
+
if (DCI.isBeforeLegalizeOps())
return SDValue();
@@ -32982,8 +32992,6 @@ static SDValue combineAnd(SDNode *N, Sel
if (SDValue ShiftRight = combineAndMaskToShift(N, DAG, Subtarget))
return ShiftRight;
- EVT VT = N->getValueType(0);
-
// Attempt to recursively combine a bitmask AND with shuffles.
if (VT.isVector() && (VT.getScalarSizeInBits() % 8) == 0) {
SDValue Op(N, 0);
@@ -33266,6 +33274,18 @@ static SDValue combineOrCmpEqZeroToCtlzS
static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget &Subtarget) {
+ SDValue N0 = N->getOperand(0);
+ SDValue N1 = N->getOperand(1);
+ EVT VT = N->getValueType(0);
+
+ // If this is SSE1 only convert to FOR to avoid scalarization.
+ if (Subtarget.hasSSE1() && !Subtarget.hasSSE2() && VT == MVT::v4i32) {
+ return DAG.getBitcast(MVT::v4i32,
+ DAG.getNode(X86ISD::FOR, SDLoc(N), MVT::v4f32,
+ DAG.getBitcast(MVT::v4f32, N0),
+ DAG.getBitcast(MVT::v4f32, N1)));
+ }
+
if (DCI.isBeforeLegalizeOps())
return SDValue();
@@ -33278,10 +33298,6 @@ static SDValue combineOr(SDNode *N, Sele
if (SDValue R = combineLogicBlendIntoPBLENDV(N, DAG, Subtarget))
return R;
- SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
- EVT VT = N->getValueType(0);
-
if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
return SDValue();
@@ -34957,6 +34973,15 @@ static SDValue foldXor1SetCC(SDNode *N,
static SDValue combineXor(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget &Subtarget) {
+ // If this is SSE1 only convert to FXOR to avoid scalarization.
+ if (Subtarget.hasSSE1() && !Subtarget.hasSSE2() &&
+ N->getValueType(0) == MVT::v4i32) {
+ return DAG.getBitcast(
+ MVT::v4i32, DAG.getNode(X86ISD::FXOR, SDLoc(N), MVT::v4f32,
+ DAG.getBitcast(MVT::v4f32, N->getOperand(0)),
+ DAG.getBitcast(MVT::v4f32, N->getOperand(1))));
+ }
+
if (SDValue Cmp = foldVectorXorShiftIntoCmp(N, DAG, Subtarget))
return Cmp;
Modified: llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll?rev=318967&r1=318966&r2=318967&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll (original)
+++ llvm/trunk/test/CodeGen/X86/merge-consecutive-loads-128.ll Fri Nov 24 23:20:21 2017
@@ -1067,11 +1067,10 @@ define void @merge_4i32_i32_combine(<4 x
; X32-SSE1: # BB#0:
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X32-SSE1-NEXT: movl (%ecx), %ecx
-; X32-SSE1-NEXT: movl %ecx, (%eax)
-; X32-SSE1-NEXT: movl $0, 12(%eax)
-; X32-SSE1-NEXT: movl $0, 8(%eax)
-; X32-SSE1-NEXT: movl $0, 4(%eax)
+; X32-SSE1-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X32-SSE1-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-SSE1-NEXT: andps %xmm0, %xmm1
+; X32-SSE1-NEXT: movaps %xmm1, (%eax)
; X32-SSE1-NEXT: retl
;
; X32-SSE41-LABEL: merge_4i32_i32_combine:
Modified: llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll?rev=318967&r1=318966&r2=318967&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll Fri Nov 24 23:20:21 2017
@@ -38,66 +38,12 @@ define <4 x float> @test_mm_add_ss(<4 x
define <4 x float> @test_mm_and_ps(<4 x float> %a0, <4 x float> %a1) nounwind {
; X32-LABEL: test_mm_and_ps:
; X32: # BB#0:
-; X32-NEXT: pushl %ebp
-; X32-NEXT: movl %esp, %ebp
-; X32-NEXT: pushl %esi
-; X32-NEXT: andl $-16, %esp
-; X32-NEXT: subl $64, %esp
-; X32-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X32-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
-; X32-NEXT: andl {{[0-9]+}}(%esp), %esi
-; X32-NEXT: movl %esi, (%esp)
-; X32-NEXT: andl {{[0-9]+}}(%esp), %edx
-; X32-NEXT: movl %edx, {{[0-9]+}}(%esp)
-; X32-NEXT: andl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; X32-NEXT: andl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X32-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; X32-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
-; X32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; X32-NEXT: leal -4(%ebp), %esp
-; X32-NEXT: popl %esi
-; X32-NEXT: popl %ebp
+; X32-NEXT: andps %xmm1, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm_and_ps:
; X64: # BB#0:
-; X64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r8
-; X64-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rdx
-; X64-NEXT: movq %rdx, %rsi
-; X64-NEXT: andl %eax, %edx
-; X64-NEXT: shrq $32, %rax
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
-; X64-NEXT: movq %rcx, %rdi
-; X64-NEXT: andl %r8d, %ecx
-; X64-NEXT: shrq $32, %r8
-; X64-NEXT: shrq $32, %rsi
-; X64-NEXT: shrq $32, %rdi
-; X64-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)
-; X64-NEXT: andl %r8d, %edi
-; X64-NEXT: movl %edi, -{{[0-9]+}}(%rsp)
-; X64-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
-; X64-NEXT: andl %eax, %esi
-; X64-NEXT: movl %esi, -{{[0-9]+}}(%rsp)
-; X64-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X64-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X64-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; X64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
-; X64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; X64-NEXT: andps %xmm1, %xmm0
; X64-NEXT: retq
%arg0 = bitcast <4 x float> %a0 to <4 x i32>
%arg1 = bitcast <4 x float> %a1 to <4 x i32>
@@ -109,74 +55,14 @@ define <4 x float> @test_mm_and_ps(<4 x
define <4 x float> @test_mm_andnot_ps(<4 x float> %a0, <4 x float> %a1) nounwind {
; X32-LABEL: test_mm_andnot_ps:
; X32: # BB#0:
-; X32-NEXT: pushl %ebp
-; X32-NEXT: movl %esp, %ebp
-; X32-NEXT: pushl %esi
-; X32-NEXT: andl $-16, %esp
-; X32-NEXT: subl $64, %esp
-; X32-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X32-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
-; X32-NEXT: notl %edx
-; X32-NEXT: notl %esi
-; X32-NEXT: notl %ecx
-; X32-NEXT: notl %eax
-; X32-NEXT: andl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: movl %eax, (%esp)
-; X32-NEXT: andl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; X32-NEXT: andl {{[0-9]+}}(%esp), %esi
-; X32-NEXT: movl %esi, {{[0-9]+}}(%esp)
-; X32-NEXT: andl {{[0-9]+}}(%esp), %edx
-; X32-NEXT: movl %edx, {{[0-9]+}}(%esp)
-; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X32-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; X32-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
-; X32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; X32-NEXT: leal -4(%ebp), %esp
-; X32-NEXT: popl %esi
-; X32-NEXT: popl %ebp
+; X32-NEXT: xorps {{\.LCPI.*}}, %xmm0
+; X32-NEXT: andps %xmm1, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm_andnot_ps:
; X64: # BB#0:
-; X64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
-; X64-NEXT: movq %rcx, %rdx
-; X64-NEXT: shrq $32, %rdx
-; X64-NEXT: movq %rax, %rsi
-; X64-NEXT: shrq $32, %rsi
-; X64-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rdi
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r8
-; X64-NEXT: notl %eax
-; X64-NEXT: andl %edi, %eax
-; X64-NEXT: shrq $32, %rdi
-; X64-NEXT: notl %ecx
-; X64-NEXT: andl %r8d, %ecx
-; X64-NEXT: shrq $32, %r8
-; X64-NEXT: notl %esi
-; X64-NEXT: notl %edx
-; X64-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)
-; X64-NEXT: andl %r8d, %edx
-; X64-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
-; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
-; X64-NEXT: andl %edi, %esi
-; X64-NEXT: movl %esi, -{{[0-9]+}}(%rsp)
-; X64-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X64-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X64-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; X64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
-; X64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; X64-NEXT: xorps {{.*}}(%rip), %xmm0
+; X64-NEXT: andps %xmm1, %xmm0
; X64-NEXT: retq
%arg0 = bitcast <4 x float> %a0 to <4 x i32>
%arg1 = bitcast <4 x float> %a1 to <4 x i32>
@@ -1262,66 +1148,12 @@ define <4 x float> @test_mm_mul_ss(<4 x
define <4 x float> @test_mm_or_ps(<4 x float> %a0, <4 x float> %a1) nounwind {
; X32-LABEL: test_mm_or_ps:
; X32: # BB#0:
-; X32-NEXT: pushl %ebp
-; X32-NEXT: movl %esp, %ebp
-; X32-NEXT: pushl %esi
-; X32-NEXT: andl $-16, %esp
-; X32-NEXT: subl $64, %esp
-; X32-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X32-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
-; X32-NEXT: orl {{[0-9]+}}(%esp), %esi
-; X32-NEXT: movl %esi, (%esp)
-; X32-NEXT: orl {{[0-9]+}}(%esp), %edx
-; X32-NEXT: movl %edx, {{[0-9]+}}(%esp)
-; X32-NEXT: orl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; X32-NEXT: orl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X32-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; X32-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
-; X32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; X32-NEXT: leal -4(%ebp), %esp
-; X32-NEXT: popl %esi
-; X32-NEXT: popl %ebp
+; X32-NEXT: orps %xmm1, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm_or_ps:
; X64: # BB#0:
-; X64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r8
-; X64-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rdx
-; X64-NEXT: movq %rdx, %rsi
-; X64-NEXT: orl %eax, %edx
-; X64-NEXT: shrq $32, %rax
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
-; X64-NEXT: movq %rcx, %rdi
-; X64-NEXT: orl %r8d, %ecx
-; X64-NEXT: shrq $32, %r8
-; X64-NEXT: shrq $32, %rsi
-; X64-NEXT: shrq $32, %rdi
-; X64-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)
-; X64-NEXT: orl %r8d, %edi
-; X64-NEXT: movl %edi, -{{[0-9]+}}(%rsp)
-; X64-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
-; X64-NEXT: orl %eax, %esi
-; X64-NEXT: movl %esi, -{{[0-9]+}}(%rsp)
-; X64-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X64-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X64-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; X64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
-; X64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; X64-NEXT: orps %xmm1, %xmm0
; X64-NEXT: retq
%arg0 = bitcast <4 x float> %a0 to <4 x i32>
%arg1 = bitcast <4 x float> %a1 to <4 x i32>
@@ -2224,66 +2056,12 @@ define <4 x float> @test_mm_unpacklo_ps(
define <4 x float> @test_mm_xor_ps(<4 x float> %a0, <4 x float> %a1) nounwind {
; X32-LABEL: test_mm_xor_ps:
; X32: # BB#0:
-; X32-NEXT: pushl %ebp
-; X32-NEXT: movl %esp, %ebp
-; X32-NEXT: pushl %esi
-; X32-NEXT: andl $-16, %esp
-; X32-NEXT: subl $64, %esp
-; X32-NEXT: movaps %xmm0, {{[0-9]+}}(%esp)
-; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
-; X32-NEXT: movaps %xmm1, {{[0-9]+}}(%esp)
-; X32-NEXT: xorl {{[0-9]+}}(%esp), %esi
-; X32-NEXT: movl %esi, (%esp)
-; X32-NEXT: xorl {{[0-9]+}}(%esp), %edx
-; X32-NEXT: movl %edx, {{[0-9]+}}(%esp)
-; X32-NEXT: xorl {{[0-9]+}}(%esp), %ecx
-; X32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
-; X32-NEXT: xorl {{[0-9]+}}(%esp), %eax
-; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
-; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X32-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; X32-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
-; X32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; X32-NEXT: leal -4(%ebp), %esp
-; X32-NEXT: popl %esi
-; X32-NEXT: popl %ebp
+; X32-NEXT: xorps %xmm1, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: test_mm_xor_ps:
; X64: # BB#0:
-; X64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rax
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %r8
-; X64-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp)
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rdx
-; X64-NEXT: movq %rdx, %rsi
-; X64-NEXT: xorl %eax, %edx
-; X64-NEXT: shrq $32, %rax
-; X64-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
-; X64-NEXT: movq %rcx, %rdi
-; X64-NEXT: xorl %r8d, %ecx
-; X64-NEXT: shrq $32, %r8
-; X64-NEXT: shrq $32, %rsi
-; X64-NEXT: shrq $32, %rdi
-; X64-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)
-; X64-NEXT: xorl %r8d, %edi
-; X64-NEXT: movl %edi, -{{[0-9]+}}(%rsp)
-; X64-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
-; X64-NEXT: xorl %eax, %esi
-; X64-NEXT: movl %esi, -{{[0-9]+}}(%rsp)
-; X64-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X64-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X64-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; X64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
-; X64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; X64-NEXT: xorps %xmm1, %xmm0
; X64-NEXT: retq
%arg0 = bitcast <4 x float> %a0 to <4 x i32>
%arg1 = bitcast <4 x float> %a1 to <4 x i32>
Modified: llvm/trunk/test/CodeGen/X86/sse1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse1.ll?rev=318967&r1=318966&r2=318967&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse1.ll Fri Nov 24 23:20:21 2017
@@ -158,56 +158,81 @@ define <4 x float> @PR28044(<4 x float>
define <4 x i32> @PR30512(<4 x i32> %x, <4 x i32> %y) nounwind {
; X32-LABEL: PR30512:
; X32: # BB#0:
-; X32-NEXT: pushl %ebp
; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %edi
; X32-NEXT: pushl %esi
-; X32-NEXT: movl {{[0-9]+}}(%esp), %ebp
+; X32-NEXT: subl $16, %esp
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
; X32-NEXT: movl {{[0-9]+}}(%esp), %edi
-; X32-NEXT: movl {{[0-9]+}}(%esp), %ebx
-; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X32-NEXT: xorl %ecx, %ecx
-; X32-NEXT: cmpl {{[0-9]+}}(%esp), %edx
-; X32-NEXT: sete %cl
-; X32-NEXT: xorl %edx, %edx
-; X32-NEXT: cmpl {{[0-9]+}}(%esp), %ebx
-; X32-NEXT: sete %dl
; X32-NEXT: xorl %ebx, %ebx
; X32-NEXT: cmpl {{[0-9]+}}(%esp), %edi
; X32-NEXT: sete %bl
-; X32-NEXT: xorl %eax, %eax
+; X32-NEXT: negl %ebx
+; X32-NEXT: movl %ebx, {{[0-9]+}}(%esp)
+; X32-NEXT: xorl %ebx, %ebx
; X32-NEXT: cmpl {{[0-9]+}}(%esp), %esi
-; X32-NEXT: sete %al
-; X32-NEXT: movl %eax, 12(%ebp)
-; X32-NEXT: movl %ebx, 8(%ebp)
-; X32-NEXT: movl %edx, 4(%ebp)
-; X32-NEXT: movl %ecx, (%ebp)
-; X32-NEXT: movl %ebp, %eax
+; X32-NEXT: sete %bl
+; X32-NEXT: negl %ebx
+; X32-NEXT: movl %ebx, {{[0-9]+}}(%esp)
+; X32-NEXT: xorl %ebx, %ebx
+; X32-NEXT: cmpl {{[0-9]+}}(%esp), %edx
+; X32-NEXT: sete %bl
+; X32-NEXT: negl %ebx
+; X32-NEXT: movl %ebx, {{[0-9]+}}(%esp)
+; X32-NEXT: xorl %edx, %edx
+; X32-NEXT: cmpl {{[0-9]+}}(%esp), %ecx
+; X32-NEXT: sete %dl
+; X32-NEXT: negl %edx
+; X32-NEXT: movl %edx, (%esp)
+; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X32-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X32-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; X32-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; X32-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0]
+; X32-NEXT: andps {{\.LCPI.*}}, %xmm2
+; X32-NEXT: movaps %xmm2, (%eax)
+; X32-NEXT: addl $16, %esp
; X32-NEXT: popl %esi
; X32-NEXT: popl %edi
; X32-NEXT: popl %ebx
-; X32-NEXT: popl %ebp
; X32-NEXT: retl $4
;
; X64-LABEL: PR30512:
; X64: # BB#0:
; X64-NEXT: xorl %eax, %eax
-; X64-NEXT: cmpl %r9d, %esi
+; X64-NEXT: cmpl {{[0-9]+}}(%rsp), %r8d
; X64-NEXT: sete %al
-; X64-NEXT: xorl %esi, %esi
-; X64-NEXT: cmpl {{[0-9]+}}(%rsp), %edx
-; X64-NEXT: sete %sil
-; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: negl %eax
+; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
+; X64-NEXT: xorl %eax, %eax
; X64-NEXT: cmpl {{[0-9]+}}(%rsp), %ecx
-; X64-NEXT: sete %dl
-; X64-NEXT: xorl %ecx, %ecx
-; X64-NEXT: cmpl {{[0-9]+}}(%rsp), %r8d
-; X64-NEXT: sete %cl
-; X64-NEXT: movl %ecx, 12(%rdi)
-; X64-NEXT: movl %edx, 8(%rdi)
-; X64-NEXT: movl %esi, 4(%rdi)
-; X64-NEXT: movl %eax, (%rdi)
+; X64-NEXT: sete %al
+; X64-NEXT: negl %eax
+; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: cmpl {{[0-9]+}}(%rsp), %edx
+; X64-NEXT: sete %al
+; X64-NEXT: negl %eax
+; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: cmpl %r9d, %esi
+; X64-NEXT: sete %al
+; X64-NEXT: negl %eax
+; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
+; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X64-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; X64-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X64-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; X64-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; X64-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0]
+; X64-NEXT: andps {{.*}}(%rip), %xmm2
+; X64-NEXT: movaps %xmm2, (%rdi)
; X64-NEXT: movq %rdi, %rax
; X64-NEXT: retq
%cmp = icmp eq <4 x i32> %x, %y
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