[PATCH] D40420: [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output

Francis Visoiu Mistrih via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Nov 24 03:33:55 PST 2017


thegameg created this revision.
Herald added subscribers: JDevlieghere, kbarton, aheejin, jgravelle-google, sbc100, javed.absar, nhaehnle, nemanjai, dschuff, arsenm, jfb, jholewinski.

As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities).


https://reviews.llvm.org/D40420

Files:
  include/llvm/CodeGen/MachineOperand.h
  include/llvm/CodeGen/TargetRegisterInfo.h
  lib/CodeGen/DetectDeadLanes.cpp
  lib/CodeGen/LiveIntervalAnalysis.cpp
  lib/CodeGen/PeepholeOptimizer.cpp
  lib/CodeGen/RegisterCoalescer.cpp
  lib/CodeGen/RenameIndependentSubregs.cpp
  lib/CodeGen/SplitKit.cpp
  lib/CodeGen/TargetRegisterInfo.cpp
  lib/Target/AArch64/AArch64InstrInfo.cpp
  lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  lib/Target/AMDGPU/SIFoldOperands.cpp
  lib/Target/AMDGPU/SIPeepholeSDWA.cpp
  lib/Target/ARM/ARMBaseInstrInfo.cpp
  lib/Target/BPF/BPFISelDAGToDAG.cpp
  lib/Target/Hexagon/HexagonBlockRanges.cpp
  lib/Target/Hexagon/HexagonConstPropagation.cpp
  lib/Target/Hexagon/HexagonEarlyIfConv.cpp
  lib/Target/Hexagon/HexagonGenInsert.cpp
  lib/Target/Hexagon/HexagonHardwareLoops.cpp
  lib/Target/Hexagon/HexagonPeephole.cpp
  lib/Target/Hexagon/HexagonStoreWidening.cpp
  lib/Target/Hexagon/HexagonSubtarget.cpp
  lib/Target/NVPTX/NVPTXPeephole.cpp
  lib/Target/PowerPC/PPCBranchCoalescing.cpp
  lib/Target/PowerPC/PPCInstrInfo.cpp
  lib/Target/PowerPC/PPCMIPeephole.cpp
  lib/Target/PowerPC/PPCVSXFMAMutate.cpp
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
  test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir
  test/CodeGen/AArch64/GlobalISel/verify-selected.mir
  test/CodeGen/AArch64/aarch64-stp-cluster.ll
  test/CodeGen/AArch64/arm64-fast-isel-rem.ll
  test/CodeGen/AArch64/arm64-ldp-cluster.ll
  test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll
  test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
  test/CodeGen/AArch64/tailcall_misched_graph.ll
  test/CodeGen/AMDGPU/lds-output-queue.ll
  test/CodeGen/AMDGPU/liveness.mir
  test/CodeGen/AMDGPU/spill-empty-live-interval.mir
  test/CodeGen/AMDGPU/subreg-intervals.mir
  test/CodeGen/ARM/2011-11-14-EarlyClobber.ll
  test/CodeGen/ARM/Windows/dbzchk.ll
  test/CodeGen/ARM/crash-greedy.ll
  test/CodeGen/ARM/misched-copy-arm.ll
  test/CodeGen/ARM/misched-int-basic-thumb2.mir
  test/CodeGen/ARM/misched-int-basic.mir
  test/CodeGen/ARM/single-issue-r52.mir
  test/CodeGen/ARM/subreg-remat.ll
  test/CodeGen/Hexagon/circ_ldd_bug.ll
  test/CodeGen/Hexagon/post-inc-aa-metadata.ll
  test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll
  test/CodeGen/PowerPC/quadint-return.ll
  test/CodeGen/WebAssembly/dbgvalue.ll
  test/CodeGen/X86/GlobalISel/x86_64-fallback.ll
  test/CodeGen/X86/cmovcmov.ll
  test/CodeGen/X86/coalescer-dce.ll
  test/CodeGen/X86/crash.ll
  test/CodeGen/X86/handle-move.ll
  test/CodeGen/X86/invalid-liveness.mir
  test/CodeGen/X86/liveness-local-regalloc.ll
  test/CodeGen/X86/misched-copy.ll
  test/CodeGen/X86/norex-subreg.ll
  test/CodeGen/X86/phys_subreg_coalesce-3.ll
  test/DebugInfo/MIR/X86/live-debug-vars-unused-arg-debugonly.mir

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