[PATCH] D39845: [TableGen] Give the option of tolerating duplicate register names

[Krzysztof Parzyszek via Phabricator via llvm-commits]

kparzysz added a comment.

This looks reasonable to me.  The only comment I have is that the patch does not make it clear what numeric register id exactly will be returned if there are several of them matching a given string.  Currently, the numeric match is unique, but once we make it non-unique, the code in a target with "reused" names will need to handle getting a "wrong" register id.  Let's take the testcase as an example---the user would need to write something like this:

  if (Want32Bit) {
    // If we got a 64-bit register, map it to the 32-bit counterpart.
    switch (Reg) {
      case R0_64:
        Reg = R0_32;
        break;
      case R1_64:
        ...
    }
  } else if (Want64Bit) {
    // If we got a 32-bit register, map it to the 64-bit counterpart.
    switch (Reg) {
      case R0_32:
        Reg = R0_64;
        break;
      case R1_32:
        ...
  }

This may be somewhat inconvenient, so I'm thinking if some extra support for this could be implemented as well.  What I have in mind is something like:

  if (Want64Bit)
   Reg = givenAnyRepresentativeGiveMeTheCorrespondingRegisterThatIWant(Reg, IWant64BitRegister);

The only issue is how to specify the "IWant64BitRegister" part.  This will be used in the asm parser, so it has to work with the MC layer alone (so, no TargetRegisterInfo, etc.), so register classes probably wouldn't work. (At first I thought about something like `getCounterpartFromRegClass(Reg, MyTarget::R64RegClass)`).  Maybe adding some kind of an extra flag to "Register" would work?

  let Namespace = "Arch" in {
  class ArchReg<string n, list <string> alt, list <RegAltNameIndex> altidx, string disambiguator>
      : Register<n, disambiguator> {
    let AltNames = alt;
    let RegAltNameIndices = altidx;
  }
  
  foreach i = 0-3 in {
    def R#i#_32 : ArchReg<"r"#i, ["x"#i], [ABIRegAltName], "32 bit">;
    def R#i#_64 : ArchReg<"r"#i, ["x"#i], [ABIRegAltName], "64 bit">;
  }

Then have TableGen generate a function like

  unsigned disambiguate(unsigned Reg, StringRef Str) {
    for (R in possible candidates)
      if (R.Disambiguator == Str)   // This is some fake syntax, but you get the idea.
        return R.Id;
  }

And in the asm parser, use it as

  if (Want64Bit)
    Reg = disambiguate(Reg, "64 bit");

It wouldn't have to be string-based, this is just an illustration.

All of this would only apply to targets that set the flag "AllowDuplicateRegisterNames", for all other targets, the disambiguating flag could be unset and ignored, and such a function wouldn't be generated.


https://reviews.llvm.org/D39845