[PATCH] D39805: [Power9] Set MicroOpBufferSize for Power 9

[Andrew Trick via Phabricator via llvm-commits]

atrick added a comment.

Think of CurrCycle as the cycle in which an instruction is issued.

With MicroOpsBufferSize = 0 (VLIW-ish): Instructions will not be scheduled until after CurrCycle >= ReadyCycle. Stalling on latency is a last resort.
With MicroOpsBufferSize = 1 (inorder): Any ready instruction may be scheduled, but it will effectively stall the issue pipe (CurrCycle = ReadyCycle). Heuristics decide when to stall.
With MicroOpsBufferSize <1(OOO): Instructions can be issued before they are ready without stalling the pipeline.
Realistically, the scheduler can't model precisely when OOO resources are full, but heuristics can take it into account.
You can add in-order resources though to model stalls for just a subset of operations (I'm not sure how well that works in practice).

Look at -debug-only=machine-schedule to see how it works.

Please add comments where you think it would be helpful. This should be more self-documenting.


https://reviews.llvm.org/D39805