[llvm] r318884 - [AArch64] Adjust the cost model for Exynos M1 and M2

[Evandro Menezes via llvm-commits]

Author: evandro
Date: Wed Nov 22 14:48:50 2017
New Revision: 318884

URL: http://llvm.org/viewvc/llvm-project?rev=318884&view=rev
Log:
[AArch64] Adjust the cost model for Exynos M1 and M2

Fix the modeling of some loads and stores.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td?rev=318884&r1=318883&r2=318884&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td Wed Nov 22 14:48:50 2017
@@ -101,18 +101,21 @@ def M1WriteL6 : SchedWriteRes<[M1UnitL]>
 def M1WriteLA : SchedWriteRes<[M1UnitL]> { let Latency = 6;
                                            let ResourceCycles = [2]; }
 def M1WriteLB : SchedWriteRes<[M1UnitL,
-                               M1UnitA]> { let Latency = 5;
+                               M1UnitA]> { let Latency = 4;
                                            let NumMicroOps = 2; }
 def M1WriteLC : SchedWriteRes<[M1UnitL,
+                               M1UnitA]> { let Latency = 5;
+                                           let NumMicroOps = 2; }
+def M1WriteLD : SchedWriteRes<[M1UnitL,
                                M1UnitA]> { let Latency = 6;
                                            let NumMicroOps = 2;
                                            let ResourceCycles = [2]; }
 def M1WriteLH : SchedWriteRes<[]>        { let Latency = 5;
                                            let NumMicroOps = 0; }
 def M1WriteLX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteL5]>,
-                                   SchedVar<NoSchedPred,         [M1WriteLB]>]>;
-def M1WriteLY : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteL5]>,
                                    SchedVar<NoSchedPred,         [M1WriteLC]>]>;
+def M1WriteLY : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteL5]>,
+                                   SchedVar<NoSchedPred,         [M1WriteLD]>]>;
 
 def M1WriteS1 : SchedWriteRes<[M1UnitS]>   { let Latency = 1; }
 def M1WriteS3 : SchedWriteRes<[M1UnitS]>   { let Latency = 3; }
@@ -124,7 +127,7 @@ def M1WriteSA : SchedWriteRes<[M1UnitS,
                                              let NumMicroOps = 2; }
 def M1WriteSB : SchedWriteRes<[M1UnitS,
                                M1UnitFST,
-                               M1UnitA]>   { let Latency = 2;
+                               M1UnitA]>   { let Latency = 3;
                                              let NumMicroOps = 2; }
 def M1WriteSC : SchedWriteRes<[M1UnitS,
                                M1UnitFST,
@@ -136,10 +139,13 @@ def M1WriteSD : SchedWriteRes<[M1UnitS,
                                M1UnitFST,
                                M1UnitA]>   { let Latency = 1;
                                              let NumMicroOps = 2; }
+def M1WriteSE : SchedWriteRes<[M1UnitS,
+                               M1UnitA]>   { let Latency = 2;
+                                             let NumMicroOps = 2; }
 def M1WriteSX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteS1]>,
-                                   SchedVar<NoSchedPred,         [M1WriteSD]>]>;
+                                   SchedVar<NoSchedPred,         [M1WriteSE]>]>;
 def M1WriteSY : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteS1]>,
-                                   SchedVar<NoSchedPred,         [M1WriteSC]>]>;
+                                   SchedVar<NoSchedPred,         [M1WriteSB]>]>;
 
 def M1ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
                                       SchedVar<NoSchedPred,   [ReadDefault]>]>;
@@ -443,10 +449,9 @@ def : InstRW<[M1WriteAX], (instregex ".+
 // Miscellaneous instructions.
 
 // Load instructions.
-def : InstRW<[WriteLD,
+def : InstRW<[M1WriteLB,
               WriteLDHi,
-              WriteAdr,
-              M1WriteA1], (instregex "^LDP(SW|W|X)(post|pre)")>;
+              WriteAdr],    (instregex "^LDP(SW|W|X)(post|pre)")>;
 def : InstRW<[M1WriteLX,
               ReadAdrBase], (instregex "^PRFMro[WX]")>;
 
@@ -486,16 +491,16 @@ def : InstRW<[WriteVLD,
 def : InstRW<[WriteVLD],    (instregex "^LDR[BDHSQ]ui")>;
 def : InstRW<[M1WriteLY,
               ReadAdrBase], (instregex "^LDR[BDHS]ro[WX]")>;
-def : InstRW<[M1WriteLY,
+def : InstRW<[M1WriteLD,
               ReadAdrBase], (instregex "^LDRQro[WX]")>;
 def : InstRW<[WriteVLD,
               M1WriteLH],   (instregex "^LDN?P[DS]i")>;
 def : InstRW<[M1WriteLA,
               M1WriteLH],   (instregex "^LDN?PQi")>;
-def : InstRW<[M1WriteLB,
+def : InstRW<[M1WriteLC,
               M1WriteLH,
               WriteAdr],    (instregex "^LDP[DS](post|pre)")>;
-def : InstRW<[M1WriteLC,
+def : InstRW<[M1WriteLD,
               M1WriteLH,
               WriteAdr],    (instregex "^LDPQ(post|pre)")>;