[llvm] r318876 - [Hexagon] Add patterns to select A2_combine_ll and its variants

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Nov 22 12:55:41 2017
New Revision: 318876

URL: http://llvm.org/viewvc/llvm-project?rev=318876&view=rev
Log:
[Hexagon] Add patterns to select A2_combine_ll and its variants

Added:
    llvm/trunk/test/CodeGen/Hexagon/isel-combine-half.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
    llvm/trunk/test/CodeGen/Hexagon/isel-prefer.ll

Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td?rev=318876&r1=318875&r2=318876&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td Wed Nov 22 12:55:41 2017
@@ -1130,6 +1130,16 @@ def: Pat<(or (or (shl (or (shl (i32 (ext
              (zextloadi8 I32:$b)),
          (A2_swiz (L2_loadri_io IntRegs:$b, 0))>;
 
+let AddedComplexity = 200 in {
+  def: Pat<(or (shl I32:$Rt, (i32 16)), (and I32:$Rs, (i32 65535))),
+           (A2_combine_ll I32:$Rt, I32:$Rs)>;
+  def: Pat<(or (shl I32:$Rt, (i32 16)), (srl I32:$Rs, (i32 16))),
+           (A2_combine_lh I32:$Rt, I32:$Rs)>;
+  def: Pat<(or (and I32:$Rt, (i32 268431360)), (and I32:$Rs, (i32 65535))),
+           (A2_combine_hl I32:$Rt, I32:$Rs)>;
+  def: Pat<(or (and I32:$Rt, (i32 268431360)), (srl I32:$Rs, (i32 16))),
+           (A2_combine_hh I32:$Rt, I32:$Rs)>;
+}
 
 def SDTHexagonVShift
   : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVec<0>, SDTCisVT<2, i32>]>;

Added: llvm/trunk/test/CodeGen/Hexagon/isel-combine-half.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/isel-combine-half.ll?rev=318876&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/isel-combine-half.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/isel-combine-half.ll Wed Nov 22 12:55:41 2017
@@ -0,0 +1,43 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK-LABEL: A2_combine_ll:
+; CHECK: combine(r1.l,r0.l)
+define i32 @A2_combine_ll(i32 %a0, i32 %a1) #0 {
+b2:
+  %v3 = and i32 %a0, 65535
+  %v4 = shl i32 %a1, 16
+  %v5 = or i32 %v3, %v4
+  ret i32 %v5
+}
+
+; CHECK-LABEL: A2_combine_lh:
+; CHECK: combine(r1.l,r0.h)
+define i32 @A2_combine_lh(i32 %a0, i32 %a1) #0 {
+b2:
+  %v3 = lshr i32 %a0, 16
+  %v4 = shl i32 %a1, 16
+  %v5 = or i32 %v4, %v3
+  ret i32 %v5
+}
+
+; CHECK-LABEL: A2_combine_hl:
+; CHECK: combine(r1.h,r0.l)
+define i32 @A2_combine_hl(i32 %a0, i32 %a1) #0 {
+b2:
+  %v3 = and i32 %a0, 65535
+  %v4 = and i32 %a1, 268431360
+  %v5 = or i32 %v3, %v4
+  ret i32 %v5
+}
+
+; CHECK-LABEL: A2_combine_hh:
+; CHECK: combine(r1.h,r0.h)
+define i32 @A2_combine_hh(i32 %a0, i32 %a1) #0 {
+b2:
+  %v3 = lshr i32 %a0, 16
+  %v4 = and i32 %a1, 268431360
+  %v5 = or i32 %v3, %v4
+  ret i32 %v5
+}
+
+attributes #0 = { noinline nounwind optnone readnone }

Modified: llvm/trunk/test/CodeGen/Hexagon/isel-prefer.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/isel-prefer.ll?rev=318876&r1=318875&r2=318876&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/isel-prefer.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/isel-prefer.ll Wed Nov 22 12:55:41 2017
@@ -64,4 +64,4 @@ b1:
   ret i64 %v4
 }
 
-attributes #0 = { nounwind readnone }
+attributes #0 = { optnone noinline nounwind readnone }