[PATCH] D40343: AMDGPU: Do not combine loads/store across physreg defs

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

As far as I understand that is only a concern if defined register is M0 since it is read by the ds_* instructions. I.e. it should be better to check to M0, not just any physreg.
Also this should not be a concern on GFX9 since we have lds instructions which do not read M0 there (check Subtarget->ldsRequiresM0Init()).


https://reviews.llvm.org/D40343