[PATCH] D39078: [PowerPC] Relax the checking on AND/AND8 in isSignOrZeroExtended

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

LGTM.
I think this code may be off by default at this time due to issues on some external benchmarks. If that's the case, it should be fine to commit this, but you'll probably need the flag in the test case to enable the transformation that uses this.



================
Comment at: lib/Target/PowerPC/PPCInstrInfo.cpp:2336
+
+    if (!MI.getOperand(1).isReg() || !MI.getOperand(2).isReg())
+      return false;
----------------
Please turn this into an assert. If we have non-register input operands to a reg+reg instruction, it's an error and we shouldn't just continue.


Repository:
  rL LLVM

https://reviews.llvm.org/D39078