[PATCH] D40001: [RISCV] MC layer support for the load/store instructions of standard compress instruction set

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

Hi Shiva, now I've got this building on top of head I see I was incorrect to suggest removing the RISCVInstrInfo.cpp changes, as you get assertions in some of the tests if you don't. I haven't done much work with cases like this where you have multiple register classes with overlapping contents but I _think_ the most correct fix to storeRegToStackSlot and loadRegtoStackSlot is to use `if (RISCV::GPRRegClass.hasSubClassEq(RC))` rather than `if (RC == &RISCV::GPRRegClasss)`. The original code probably should have been written using this in the first place.


https://reviews.llvm.org/D40001