[llvm] r318398 - [ARM GlobalISel] Add tests for BIC. NFC

[Diana Picus via llvm-commits]

Hi Eli,

This is supposed to test the code generated by TableGen for
defm BIC   : AsI1_bin_irs<0b1110, "bic",
                          IIC_iBITi, IIC_iBITr, IIC_iBITsr,
                          BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
where 'not' is a 'xor' with -1 (we don't have a G_NOT opcode).

I agree that it looks weird and not very likely to occur much in
practice, but I think it's useful for making sure that TableGen does
what we'd expect for AsI1_bin_irs with a BinOpFrag as opposed to just
a simple node like the other AsI1_bin_irs patterns.

Cheers,
Diana

On 16 November 2017 at 20:27, Friedman, Eli <efriedma at codeaurora.org> wrote:
> On 11/16/2017 5:32 AM, Diana Picus via llvm-commits wrote:
>>
>> Author: rovka
>> Date: Thu Nov 16 05:32:47 2017
>> New Revision: 318398
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=318398&view=rev
>> Log:
>> [ARM GlobalISel] Add tests for BIC. NFC
>>
>> +---
>> +name:            test_bicri_commutative_xor
>> +# CHECK-LABEL: name: test_bicri_commutative_xor
>> +legalized:       true
>> +regBankSelected: true
>> +selected:        false
>> +# CHECK: selected: true
>> +registers:
>> +  - { id: 0, class: gprb }
>> +  - { id: 1, class: gprb }
>> +  - { id: 2, class: gprb }
>> +  - { id: 3, class: gprb }
>> +  - { id: 4, class: gprb }
>> +body:             |
>> +  bb.0:
>> +    liveins: %r0
>> +
>> +    %0(s32) = COPY %r0
>> +    ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
>> +
>> +    %1(s32) = G_CONSTANT i32 192
>> +
>> +    %2(s32) = G_CONSTANT i32 -1
>> +    %3(s32) = G_XOR %2, %1
>> +    %4(s32) = G_AND %0, %3
>> +    ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, _, _
>
>
> This is a weird way to write this test.  Why not just write "G_CONSTANT i32
> -193"?
>
> -Eli
>
> --
> Employee of Qualcomm Innovation Center, Inc.
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux
> Foundation Collaborative Project
>