[PATCH] D40227: [Hexagon] Use stable sort for HexagonShuffler to remove non-deterministic ordering

[Mandeep Singh Grang via Phabricator via llvm-commits]

mgrang created this revision.

This fixes failures in the following tests uncovered by https://reviews.llvm.org/D39245:

  LLVM :: CodeGen/Hexagon/args.ll
  LLVM :: CodeGen/Hexagon/constp-extract.ll
  LLVM :: CodeGen/Hexagon/expand-condsets-basic.ll
  LLVM :: CodeGen/Hexagon/gp-rel.ll
  LLVM :: CodeGen/Hexagon/packetize_cond_inst.ll
  LLVM :: CodeGen/Hexagon/simple_addend.ll
  LLVM :: CodeGen/Hexagon/swp-stages4.ll
  LLVM :: CodeGen/Hexagon/swp-vmult.ll
  LLVM :: CodeGen/Hexagon/swp-vsum.ll
  LLVM :: MC/Hexagon/align.s
  LLVM :: MC/Hexagon/asmMap.s
  LLVM :: MC/Hexagon/dis-duplex-p0.s
  LLVM :: MC/Hexagon/double-vector-producer.s
  LLVM :: MC/Hexagon/inst_select.ll
  LLVM :: MC/Hexagon/instructions/j.s


Repository:
  rL LLVM

https://reviews.llvm.org/D40227

Files:
  lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp


Index: lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
===================================================================
--- lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
+++ lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
@@ -465,7 +465,7 @@
       foundBranches[1]->Core.setUnits(jumpSlots[i].second);
 
       HexagonUnitAuction AuctionCore(reservedSlots);
-      std::sort(begin(), end(), HexagonInstr::lessCore);
+      std::stable_sort(begin(), end(), HexagonInstr::lessCore);
 
       // see if things ok with that instruction being pinned to slot "slotJump"
       bool bFail = false;
@@ -495,7 +495,7 @@
     slot3ISJ->Core.setUnits(saveUnits & slotThree);
 
     HexagonUnitAuction AuctionCore(reservedSlots);
-    std::sort(begin(), end(), HexagonInstr::lessCore);
+    std::stable_sort(begin(), end(), HexagonInstr::lessCore);
 
     // see if things ok with that instruction being pinned to slot #3
     bool bFail = false;
@@ -519,16 +519,16 @@
   if (validateSlots) {
     HexagonUnitAuction AuctionCore(reservedSlots);
 
-    std::sort(begin(), end(), HexagonInstr::lessCore);
+    std::stable_sort(begin(), end(), HexagonInstr::lessCore);
 
     for (iterator I = begin(); I != end(); ++I)
       if (!AuctionCore.bid(I->Core.getUnits())) {
         reportError(Twine("invalid instruction packet: slot error"));
         return false;
       }
   }
   // Verify the CVI slot subscriptions.
-  std::sort(begin(), end(), HexagonInstr::lessCVI);
+  std::stable_sort(begin(), end(), HexagonInstr::lessCVI);
   // create vector of hvx instructions to check
   HVXInstsT hvxInsts;
   hvxInsts.clear();
@@ -584,7 +584,7 @@
       if (slotWeight)
         // Sort the packet, favoring source order,
         // beginning after the previous slot.
-        std::sort(ISJ, Packet.end());
+        std::stable_sort(ISJ, Packet.end());
       else
         // Skip unused slot.
         ++emptySlots;


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