[llvm] r318526 - [AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 17 07:15:40 PST 2017
Author: dpreobra
Date: Fri Nov 17 07:15:40 2017
New Revision: 318526
URL: http://llvm.org/viewvc/llvm-project?rev=318526&view=rev
Log:
[AMDGPU][MC][GFX9][disassembler] Corrected decoding of op_sel_hi for v_mad_mix*
See bug 35148: https://bugs.llvm.org//show_bug.cgi?id=35148
Reviewers: tamazov, SamWot, arsenm
Differential Revision: https://reviews.llvm.org/D39492
Modified:
llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
llvm/trunk/lib/Target/AMDGPU/SIDefines.h
llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td
llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td
llvm/trunk/test/CodeGen/AMDGPU/mad-mix-hi.ll
llvm/trunk/test/CodeGen/AMDGPU/mad-mix-lo.ll
llvm/trunk/test/CodeGen/AMDGPU/mad-mix.ll
llvm/trunk/test/MC/AMDGPU/vop3p.s
llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=318526&r1=318525&r2=318526&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Fri Nov 17 07:15:40 2017
@@ -1077,10 +1077,7 @@ public:
OptionalImmIndexMap &OptionalIdx);
void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);
void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
- void cvtVOP3PImpl(MCInst &Inst, const OperandVector &Operands,
- bool IsPacked);
void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
- void cvtVOP3P_NotPacked(MCInst &Inst, const OperandVector &Operands);
void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
@@ -4320,11 +4317,13 @@ void AMDGPUAsmParser::cvtVOP3(MCInst &In
cvtVOP3(Inst, Operands, OptionalIdx);
}
-void AMDGPUAsmParser::cvtVOP3PImpl(MCInst &Inst,
- const OperandVector &Operands,
- bool IsPacked) {
+void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst,
+ const OperandVector &Operands) {
OptionalImmIndexMap OptIdx;
- int Opc = Inst.getOpcode();
+ const int Opc = Inst.getOpcode();
+ const MCInstrDesc &Desc = MII.get(Opc);
+
+ const bool IsPacked = (Desc.TSFlags & SIInstrFlags::IsPacked) != 0;
cvtVOP3(Inst, Operands, OptIdx);
@@ -4340,7 +4339,6 @@ void AMDGPUAsmParser::cvtVOP3PImpl(MCIns
int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);
if (OpSelHiIdx != -1) {
- // TODO: Should we change the printing to match?
int DefaultVal = IsPacked ? -1 : 0;
addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi,
DefaultVal);
@@ -4402,15 +4400,6 @@ void AMDGPUAsmParser::cvtVOP3PImpl(MCIns
}
}
-void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {
- cvtVOP3PImpl(Inst, Operands, true);
-}
-
-void AMDGPUAsmParser::cvtVOP3P_NotPacked(MCInst &Inst,
- const OperandVector &Operands) {
- cvtVOP3PImpl(Inst, Operands, false);
-}
-
//===----------------------------------------------------------------------===//
// dpp
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp?rev=318526&r1=318525&r2=318526&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp Fri Nov 17 07:15:40 2017
@@ -806,8 +806,8 @@ void AMDGPUInstPrinter::printExpTgt(cons
}
static bool allOpsDefaultValue(const int* Ops, int NumOps, int Mod,
- bool HasDstSel) {
- int DefaultValue = (Mod == SISrcMods::OP_SEL_1);
+ bool IsPacked, bool HasDstSel) {
+ int DefaultValue = IsPacked && (Mod == SISrcMods::OP_SEL_1);
for (int I = 0; I < NumOps; ++I) {
if (!!(Ops[I] & Mod) != DefaultValue)
@@ -843,7 +843,10 @@ void AMDGPUInstPrinter::printPackedModif
Mod == SISrcMods::OP_SEL_0 &&
MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
- if (allOpsDefaultValue(Ops, NumOps, Mod, HasDstSel))
+ const bool IsPacked =
+ MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
+
+ if (allOpsDefaultValue(Ops, NumOps, Mod, IsPacked, HasDstSel))
return;
O << Name;
Modified: llvm/trunk/lib/Target/AMDGPU/SIDefines.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIDefines.h?rev=318526&r1=318525&r2=318526&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIDefines.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIDefines.h Fri Nov 17 07:15:40 2017
@@ -82,7 +82,10 @@ enum : uint64_t {
// Clamps hi component of register.
// ClampLo and ClampHi set for packed clamp.
- ClampHi = UINT64_C(1) << 48
+ ClampHi = UINT64_C(1) << 48,
+
+ // Is a packed VOP3P instruction.
+ IsPacked = UINT64_C(1) << 49
};
// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td?rev=318526&r1=318525&r2=318526&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td Fri Nov 17 07:15:40 2017
@@ -115,6 +115,9 @@ class InstSI <dag outs, dag ins, string
// of a packed output register.
field bit ClampHi = 0;
+ // This bit indicates that this is a packed VOP3P instruction
+ field bit IsPacked = 0;
+
// These need to be kept in sync with the enum in SIInstrFlags.
let TSFlags{0} = SALU;
let TSFlags{1} = VALU;
@@ -168,6 +171,8 @@ class InstSI <dag outs, dag ins, string
let TSFlags{47} = ClampLo;
let TSFlags{48} = ClampHi;
+ let TSFlags{49} = IsPacked;
+
let SchedRW = [Write32Bit];
field bits<1> DisableSIDecoder = 0;
Modified: llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td?rev=318526&r1=318525&r2=318526&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOPInstructions.td Fri Nov 17 07:15:40 2017
@@ -80,6 +80,7 @@ class VOP3_Pseudo <string opName, VOPPro
let isCodeGenOnly = 1;
let UseNamedOperandTable = 1;
let VOP3_OPSEL = isVop3OpSel;
+ let IsPacked = P.IsPacked;
string Mnemonic = opName;
string AsmOperands = !if(isVop3OpSel,
@@ -114,12 +115,11 @@ class VOP3_Pseudo <string opName, VOPPro
let AsmVariantName = AMDGPUAsmVariants.VOP3;
let AsmMatchConverter =
- !if(!and(P.IsPacked, isVOP3P),
+ !if(isVOP3P,
"cvtVOP3P",
- !if(isVOP3P, "cvtVOP3P_NotPacked",
- !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)),
- "cvtVOP3",
- "")));
+ !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)),
+ "cvtVOP3",
+ ""));
VOPProfile Pfl = P;
}
Modified: llvm/trunk/test/CodeGen/AMDGPU/mad-mix-hi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/mad-mix-hi.ll?rev=318526&r1=318525&r2=318526&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/mad-mix-hi.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/mad-mix-hi.ll Fri Nov 17 07:15:40 2017
@@ -83,7 +83,7 @@ define i32 @v_mad_mixhi_f16_f16lo_f16lo_
}
; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt:
-; GFX9: v_mad_mix_f32 v0, v0, v1, v2 clamp{{$}}
+; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp{{$}}
; GFX9: v_cvt_f16_f32_e32 v0, v0
define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_precvt(half %src0, half %src1, half %src2) #0 {
%src0.ext = fpext half %src0 to float
@@ -99,7 +99,7 @@ define <2 x half> @v_mad_mixhi_f16_f16lo
; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt:
; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 clamp{{$}}
+; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp{{$}}
; GFX9-NEXT: s_setpc_b64
define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt(half %src0, half %src1, half %src2) #0 {
%src0.ext = fpext half %src0 to float
@@ -116,9 +116,9 @@ define <2 x half> @v_mad_mixhi_f16_f16lo
; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use:
; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2{{$}}
+; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]{{$}}
; GFX9-NEXT: global_store_short v{{\[[0-9]+:[0-9]+\]}}, v3
-; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 clamp{{$}}
+; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp{{$}}
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64
define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use(half %src0, half %src1, half %src2) #0 {
Modified: llvm/trunk/test/CodeGen/AMDGPU/mad-mix-lo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/mad-mix-lo.ll?rev=318526&r1=318525&r2=318526&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/mad-mix-lo.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/mad-mix-lo.ll Fri Nov 17 07:15:40 2017
@@ -4,7 +4,7 @@
; GCN-LABEL: mixlo_simple:
; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[0,0,0]{{$}}
+; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2{{$}}
; GFX9-NEXT: s_setpc_b64
; CIVI: v_mac_f32_e32
@@ -16,7 +16,7 @@ define half @mixlo_simple(float %src0, f
}
; GCN-LABEL: {{^}}v_mad_mixlo_f16_f16lo_f16lo_f16lo:
-; GFX9: v_mad_mixlo_f16 v0, v0, v1, v2{{$}}
+; GFX9: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]{{$}}
; CI: v_mac_f32
; CIVI: v_cvt_f16_f32
define half @v_mad_mixlo_f16_f16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
@@ -79,8 +79,8 @@ define half @v_mad_mixlo_f16_f16lo_f16lo
; operation only clobbers relevant lane.
; GCN-LABEL: {{^}}v_mad_mix_v2f32:
; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2{{$}}
-; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1]{{$}}
+; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]{{$}}
+; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]{{$}}
; GFX9-NEXT: v_mov_b32_e32 v0, v3
; GFX9-NEXT: s_setpc_b64
define <2 x half> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
@@ -94,9 +94,9 @@ define <2 x half> @v_mad_mix_v2f32(<2 x
; GCN-LABEL: {{^}}v_mad_mix_v3f32:
; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v3, v6
-; GFX9-NEXT: v_mad_mixlo_f16 v1, v1, v4, v7
-; GFX9-NEXT: v_mad_mixlo_f16 v2, v2, v5, v8
+; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v3, v6 op_sel_hi:[1,1,1]
+; GFX9-NEXT: v_mad_mixlo_f16 v1, v1, v4, v7 op_sel_hi:[1,1,1]
+; GFX9-NEXT: v_mad_mixlo_f16 v2, v2, v5, v8 op_sel_hi:[1,1,1]
; GFX9-NEXT: s_setpc_b64
define <3 x half> @v_mad_mix_v3f32(<3 x half> %src0, <3 x half> %src1, <3 x half> %src2) #0 {
%src0.ext = fpext <3 x half> %src0 to <3 x float>
@@ -109,10 +109,10 @@ define <3 x half> @v_mad_mix_v3f32(<3 x
; GCN-LABEL: {{^}}v_mad_mix_v4f32:
; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixlo_f16 v6, v0, v2, v4
-; GFX9-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1]
-; GFX9-NEXT: v_mad_mixlo_f16 v2, v1, v3, v5
-; GFX9-NEXT: v_mad_mixhi_f16 v2, v1, v3, v5 op_sel:[1,1,1]
+; GFX9-NEXT: v_mad_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
+; GFX9-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GFX9-NEXT: v_mad_mixlo_f16 v2, v1, v3, v5 op_sel_hi:[1,1,1]
+; GFX9-NEXT: v_mad_mixhi_f16 v2, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1]
; GFX9-NEXT: v_mov_b32_e32 v0, v6
; GFX9-NEXT: v_mov_b32_e32 v1, v2
; GFX9-NEXT: s_setpc_b64
@@ -127,8 +127,8 @@ define <4 x half> @v_mad_mix_v4f32(<4 x
; FIXME: Fold clamp
; GCN-LABEL: {{^}}v_mad_mix_v2f32_clamp_postcvt:
-; GFX9: v_mad_mixlo_f16 v3, v0, v1, v2 clamp{{$}}
-; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] clamp{{$}}
+; GFX9: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp{{$}}
+; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp{{$}}
; GFX9-NEXT: v_mov_b32_e32 v0, v3
; GFX9-NEXT: s_setpc_b64
define <2 x half> @v_mad_mix_v2f32_clamp_postcvt(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
@@ -145,10 +145,10 @@ define <2 x half> @v_mad_mix_v2f32_clamp
; FIXME: Should be packed into 2 registers per argument?
; GCN-LABEL: {{^}}v_mad_mix_v3f32_clamp_postcvt:
; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixlo_f16 v2, v2, v5, v8 clamp
-; GFX9-NEXT: v_mad_mixhi_f16 v2, v0, v0, v0 op_sel_hi:[0,0,0] clamp
-; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v3, v6 clamp
-; GFX9-NEXT: v_mad_mixhi_f16 v0, v1, v4, v7 clamp
+; GFX9-NEXT: v_mad_mixlo_f16 v2, v2, v5, v8 op_sel_hi:[1,1,1] clamp
+; GFX9-NEXT: v_mad_mixhi_f16 v2, v0, v0, v0 clamp
+; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v3, v6 op_sel_hi:[1,1,1] clamp
+; GFX9-NEXT: v_mad_mixhi_f16 v0, v1, v4, v7 op_sel_hi:[1,1,1] clamp
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX9-NEXT: s_setpc_b64
define <3 x half> @v_mad_mix_v3f32_clamp_postcvt(<3 x half> %src0, <3 x half> %src1, <3 x half> %src2) #0 {
@@ -164,10 +164,10 @@ define <3 x half> @v_mad_mix_v3f32_clamp
; GCN-LABEL: {{^}}v_mad_mix_v4f32_clamp_postcvt:
; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixlo_f16 v6, v0, v2, v4 clamp
-; GFX9-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] clamp
-; GFX9-NEXT: v_mad_mixlo_f16 v2, v1, v3, v5 clamp
-; GFX9-NEXT: v_mad_mixhi_f16 v2, v1, v3, v5 op_sel:[1,1,1] clamp
+; GFX9-NEXT: v_mad_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GFX9-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GFX9-NEXT: v_mad_mixlo_f16 v2, v1, v3, v5 op_sel_hi:[1,1,1] clamp
+; GFX9-NEXT: v_mad_mixhi_f16 v2, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GFX9-DAG: v_mov_b32_e32 v0, v6
; GFX9-DAG: v_mov_b32_e32 v1, v2
; GFX9: s_setpc_b64
@@ -184,8 +184,8 @@ define <4 x half> @v_mad_mix_v4f32_clamp
; GCN-LABEL: {{^}}v_mad_mix_v2f32_clamp_postcvt_lo:
; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2 clamp
-; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1]
+; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
; GFX9-NEXT: v_mov_b32_e32 v0, v3
; GFX9-NEXT: s_setpc_b64
define <2 x half> @v_mad_mix_v2f32_clamp_postcvt_lo(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
@@ -203,8 +203,8 @@ define <2 x half> @v_mad_mix_v2f32_clamp
; GCN-LABEL: {{^}}v_mad_mix_v2f32_clamp_postcvt_hi:
; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2
-; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] clamp
+; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GFX9-NEXT: v_mov_b32_e32 v0, v3
; GFX9-NEXT: s_setpc_b64
define <2 x half> @v_mad_mix_v2f32_clamp_postcvt_hi(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
@@ -222,8 +222,8 @@ define <2 x half> @v_mad_mix_v2f32_clamp
; FIXME: Should be able to use mixlo/mixhi
; GCN-LABEL: {{^}}v_mad_mix_v2f32_clamp_precvt:
-; GFX9: v_mad_mix_f32 v3, v0, v1, v2 clamp
-; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] clamp
+; GFX9: v_mad_mix_f32 v3, v0, v1, v2 op_sel_hi:[1,1,1] clamp
+; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
; GFX9: v_cvt_f16_f32_e32 v1, v3
; GFX9: v_cvt_f16_f32_e32 v0, v0
; GFX9: v_and_b32_e32 v1, 0xffff, v1
@@ -241,9 +241,9 @@ define <2 x half> @v_mad_mix_v2f32_clamp
}
; GCN-LABEL: {{^}}v_mad_mix_v3f32_clamp_precvt:
-; GFX9: v_mad_mix_f32 v0, v0, v3, v6 clamp
-; GFX9: v_mad_mix_f32 v1, v1, v4, v7 clamp
-; GFX9: v_mad_mix_f32 v2, v2, v5, v8 clamp
+; GFX9: v_mad_mix_f32 v0, v0, v3, v6 op_sel_hi:[1,1,1] clamp
+; GFX9: v_mad_mix_f32 v1, v1, v4, v7 op_sel_hi:[1,1,1] clamp
+; GFX9: v_mad_mix_f32 v2, v2, v5, v8 op_sel_hi:[1,1,1] clamp
; GFX9: v_cvt_f16_f32
; GFX9: v_cvt_f16_f32
; GFX9: v_cvt_f16_f32
@@ -259,10 +259,10 @@ define <3 x half> @v_mad_mix_v3f32_clamp
}
; GCN-LABEL: {{^}}v_mad_mix_v4f32_clamp_precvt:
-; GFX9: v_mad_mix_f32 v6, v0, v2, v4 op_sel:[1,1,1] clamp
-; GFX9: v_mad_mix_f32 v0, v0, v2, v4 clamp
-; GFX9: v_mad_mix_f32 v2, v1, v3, v5 op_sel:[1,1,1] clamp
-; GFX9: v_mad_mix_f32 v1, v1, v3, v5 clamp
+; GFX9: v_mad_mix_f32 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GFX9: v_mad_mix_f32 v0, v0, v2, v4 op_sel_hi:[1,1,1] clamp
+; GFX9: v_mad_mix_f32 v2, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
+; GFX9: v_mad_mix_f32 v1, v1, v3, v5 op_sel_hi:[1,1,1] clamp
; GFX9: v_cvt_f16_f32
; GFX9: v_cvt_f16_f32
; GFX9: v_cvt_f16_f32
Modified: llvm/trunk/test/CodeGen/AMDGPU/mad-mix.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/mad-mix.ll?rev=318526&r1=318525&r2=318526&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/mad-mix.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/mad-mix.ll Fri Nov 17 07:15:40 2017
@@ -3,7 +3,7 @@
; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,CI %s
; GCN-LABEL: {{^}}v_mad_mix_f32_f16lo_f16lo_f16lo:
-; GFX9: v_mad_mix_f32 v0, v0, v1, v2 ; encoding: [0x00,0x40,0xa0,0xd3,0x00,0x03,0x0a,0x1c]
+; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] ; encoding: [0x00,0x40,0xa0,0xd3,0x00,0x03,0x0a,0x1c]
; VI: v_mac_f32
; CI: v_mad_f32
define float @v_mad_mix_f32_f16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
@@ -15,7 +15,7 @@ define float @v_mad_mix_f32_f16lo_f16lo_
}
; GCN-LABEL: {{^}}v_mad_mix_f32_f16hi_f16hi_f16hi_int:
-; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] ; encoding
+; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] ; encoding
; CIVI: v_mac_f32
define float @v_mad_mix_f32_f16hi_f16hi_f16hi_int(i32 %src0, i32 %src1, i32 %src2) #0 {
%src0.hi = lshr i32 %src0, 16
@@ -35,7 +35,7 @@ define float @v_mad_mix_f32_f16hi_f16hi_
}
; GCN-LABEL: {{^}}v_mad_mix_f32_f16hi_f16hi_f16hi_elt:
-; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] ; encoding
+; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] ; encoding
; VI: v_mac_f32
; CI: v_mad_f32
define float @v_mad_mix_f32_f16hi_f16hi_f16hi_elt(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
@@ -51,8 +51,8 @@ define float @v_mad_mix_f32_f16hi_f16hi_
; GCN-LABEL: {{^}}v_mad_mix_v2f32:
; GFX9: v_mov_b32_e32 v3, v1
-; GFX9-NEXT: v_mad_mix_f32 v1, v0, v3, v2 op_sel:[1,1,1]
-; GFX9-NEXT: v_mad_mix_f32 v0, v0, v3, v2
+; GFX9-NEXT: v_mad_mix_f32 v1, v0, v3, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]
+; GFX9-NEXT: v_mad_mix_f32 v0, v0, v3, v2 op_sel_hi:[1,1,1]
; CIVI: v_mac_f32
define <2 x float> @v_mad_mix_v2f32(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
@@ -66,8 +66,8 @@ define <2 x float> @v_mad_mix_v2f32(<2 x
; GCN-LABEL: {{^}}v_mad_mix_v2f32_shuffle:
; GCN: s_waitcnt
; GFX9-NEXT: v_mov_b32_e32 v3, v1
-; GFX9-NEXT: v_mad_mix_f32 v1, v0, v3, v2 op_sel:[0,1,1]
-; GFX9-NEXT: v_mad_mix_f32 v0, v0, v3, v2 op_sel:[1,0,1]
+; GFX9-NEXT: v_mad_mix_f32 v1, v0, v3, v2 op_sel:[0,1,1] op_sel_hi:[1,1,1]
+; GFX9-NEXT: v_mad_mix_f32 v0, v0, v3, v2 op_sel:[1,0,1] op_sel_hi:[1,1,1]
; GFX9-NEXT: s_setpc_b64
; CIVI: v_mac_f32
@@ -84,7 +84,7 @@ define <2 x float> @v_mad_mix_v2f32_shuf
; GCN-LABEL: {{^}}v_mad_mix_f32_negf16lo_f16lo_f16lo:
; GFX9: s_waitcnt
-; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 ; encoding
+; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1] ; encoding
; GFX9-NEXT: s_setpc_b64
; CIVI: v_mad_f32
@@ -98,7 +98,7 @@ define float @v_mad_mix_f32_negf16lo_f16
}
; GCN-LABEL: {{^}}v_mad_mix_f32_absf16lo_f16lo_f16lo:
-; GFX9: v_mad_mix_f32 v0, |v0|, v1, v2
+; GFX9: v_mad_mix_f32 v0, |v0|, v1, v2 op_sel_hi:[1,1,1]
; CIVI: v_mad_f32
define float @v_mad_mix_f32_absf16lo_f16lo_f16lo(half %src0, half %src1, half %src2) #0 {
@@ -112,7 +112,7 @@ define float @v_mad_mix_f32_absf16lo_f16
; GCN-LABEL: {{^}}v_mad_mix_f32_negabsf16lo_f16lo_f16lo:
; GFX9: s_waitcnt
-; GFX9-NEXT: v_mad_mix_f32 v0, -|v0|, v1, v2
+; GFX9-NEXT: v_mad_mix_f32 v0, -|v0|, v1, v2 op_sel_hi:[1,1,1]
; GFX9-NEXT: s_setpc_b64
; CIVI: v_mad_f32
@@ -282,7 +282,7 @@ define <2 x float> @v_mad_mix_v2f32_f32i
}
; GCN-LABEL: {{^}}v_mad_mix_clamp_f32_f16hi_f16hi_f16hi_elt:
-; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] clamp ; encoding
+; GFX9: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp ; encoding
; VI: v_mac_f32_e64 v{{[0-9]}}, v{{[0-9]}}, v{{[0-9]}} clamp{{$}}
; CI: v_mad_f32 v{{[0-9]}}, v{{[0-9]}}, v{{[0-9]}}, v{{[0-9]}} clamp{{$}}
define float @v_mad_mix_clamp_f32_f16hi_f16hi_f16hi_elt(<2 x half> %src0, <2 x half> %src1, <2 x half> %src2) #0 {
@@ -375,7 +375,7 @@ define float @v_mad_mix_f32_f16lo_f16lo_
; GCN-LABEL: {{^}}v_mad_mix_f32_f16lo_f16lo_f16lo_f32_flush_fmulfadd:
; GCN: s_waitcnt
-; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 ; encoding
+; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,1] ; encoding
; GFX9-NEXT: s_setpc_b64
define float @v_mad_mix_f32_f16lo_f16lo_f16lo_f32_flush_fmulfadd(half %src0, half %src1, half %src2) #0 {
%src0.ext = fpext half %src0 to float
@@ -400,7 +400,7 @@ define float @v_mad_mix_f32_f16lo_f16lo_
; GCN-LABEL: {{^}}v_mad_mix_f32_negprecvtf16lo_f16lo_f16lo:
; GFX9: s_waitcnt
-; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 ; encoding
+; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel_hi:[1,1,1] ; encoding
; GFX9-NEXT: s_setpc_b64
; CIVI: v_mad_f32
@@ -433,7 +433,7 @@ define float @v_mad_mix_f32_precvtnegf16
; GCN-LABEL: {{^}}v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo:
; GFX9: s_waitcnt
-; GFX9-NEXT: v_mad_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0]
+; GFX9-NEXT: v_mad_mix_f32 v0, |v0|, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
; GFX9-NEXT: s_setpc_b64
define float @v_mad_mix_f32_precvtabsf16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
@@ -448,7 +448,7 @@ define float @v_mad_mix_f32_precvtabsf16
; GCN-LABEL: {{^}}v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo:
; GFX9: s_waitcnt
-; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0]
+; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
; GFX9-NEXT: s_setpc_b64
define float @v_mad_mix_f32_preextractfneg_f16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
@@ -465,7 +465,7 @@ define float @v_mad_mix_f32_preextractfn
; GCN-LABEL: {{^}}v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo:
; GFX9: s_waitcnt
; GFX9-NEXT: v_and_b32_e32 v0, 0x7fff0000, v0
-; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,0,0]
+; GFX9-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
; GFX9-NEXT: s_setpc_b64
define float @v_mad_mix_f32_preextractfabs_f16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
@@ -482,7 +482,7 @@ define float @v_mad_mix_f32_preextractfa
; GCN-LABEL: {{^}}v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo:
; GFX9: s_waitcnt
; GFX9-NEXT: v_and_b32_e32 v0, 0x7fff0000, v0
-; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0]
+; GFX9-NEXT: v_mad_mix_f32 v0, -v0, v1, v2 op_sel:[1,0,0] op_sel_hi:[1,1,1]
; GFX9-NEXT: s_setpc_b64
define float @v_mad_mix_f32_preextractfabsfneg_f16hi_f16lo_f16lo(i32 %src0.arg, half %src1, half %src2) #0 {
%src0.arg.bc = bitcast i32 %src0.arg to <2 x half>
Modified: llvm/trunk/test/MC/AMDGPU/vop3p.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/vop3p.s?rev=318526&r1=318525&r2=318526&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/vop3p.s (original)
+++ llvm/trunk/test/MC/AMDGPU/vop3p.s Fri Nov 17 07:15:40 2017
@@ -169,78 +169,78 @@ v_pk_max_f16 v0, v1, v2
// GFX9: v_pk_max_f16 v0, v1, v2 ; encoding: [0x00,0x00,0x92,0xd3,0x01,0x05,0x02,0x18]
v_mad_mix_f32 v0, v1, v2, v3
-// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
v_mad_mixlo_f16 v0, v1, v2, v3
-// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
v_mad_mixhi_f16 v0, v1, v2, v3
-// GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
//
// Regular source modifiers on non-packed instructions
//
v_mad_mix_f32 v0, abs(v1), v2, v3
-// GFX9: v_mad_mix_f32 v0, |v1|, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, |v1|, v2, v3 ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04]
v_mad_mix_f32 v0, v1, abs(v2), v3
-// GFX9: v_mad_mix_f32 v0, v1, |v2|, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, |v2|, v3 ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04]
v_mad_mix_f32 v0, v1, v2, abs(v3)
-// GFX9: v_mad_mix_f32 v0, v1, v2, |v3| op_sel_hi:[0,0,0] ; encoding: [0x00,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, v2, |v3| ; encoding: [0x00,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x04]
v_mad_mix_f32 v0, -v1, v2, v3
-// GFX9: v_mad_mix_f32 v0, -v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x24]
+// GFX9: v_mad_mix_f32 v0, -v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x24]
v_mad_mix_f32 v0, v1, -v2, v3
-// GFX9: v_mad_mix_f32 v0, v1, -v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x44]
+// GFX9: v_mad_mix_f32 v0, v1, -v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x44]
v_mad_mix_f32 v0, v1, v2, -v3
-// GFX9: v_mad_mix_f32 v0, v1, v2, -v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x84]
+// GFX9: v_mad_mix_f32 v0, v1, v2, -v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x84]
v_mad_mix_f32 v0, -abs(v1), v2, v3
-// GFX9: v_mad_mix_f32 v0, -|v1|, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x24]
+// GFX9: v_mad_mix_f32 v0, -|v1|, v2, v3 ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x24]
v_mad_mix_f32 v0, v1, -abs(v2), v3
-// GFX9: v_mad_mix_f32 v0, v1, -|v2|, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x44]
+// GFX9: v_mad_mix_f32 v0, v1, -|v2|, v3 ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x44]
v_mad_mix_f32 v0, v1, v2, -abs(v3)
-// GFX9: v_mad_mix_f32 v0, v1, v2, -|v3| op_sel_hi:[0,0,0] ; encoding: [0x00,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x84]
+// GFX9: v_mad_mix_f32 v0, v1, v2, -|v3| ; encoding: [0x00,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x84]
v_mad_mixlo_f16 v0, abs(v1), -v2, abs(v3)
-// GFX9: v_mad_mixlo_f16 v0, |v1|, -v2, |v3| op_sel_hi:[0,0,0] ; encoding: [0x00,0x05,0xa1,0xd3,0x01,0x05,0x0e,0x44]
+// GFX9: v_mad_mixlo_f16 v0, |v1|, -v2, |v3| ; encoding: [0x00,0x05,0xa1,0xd3,0x01,0x05,0x0e,0x44]
v_mad_mixhi_f16 v0, -v1, abs(v2), -abs(v3)
-// GFX9: v_mad_mixhi_f16 v0, -v1, |v2|, -|v3| op_sel_hi:[0,0,0] ; encoding: [0x00,0x06,0xa2,0xd3,0x01,0x05,0x0e,0xa4]
+// GFX9: v_mad_mixhi_f16 v0, -v1, |v2|, -|v3| ; encoding: [0x00,0x06,0xa2,0xd3,0x01,0x05,0x0e,0xa4]
v_mad_mixlo_f16 v0, v1, v2, v3 clamp
-// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 op_sel_hi:[0,0,0] clamp ; encoding: [0x00,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 clamp ; encoding: [0x00,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04]
v_mad_mixhi_f16 v0, v1, v2, v3 clamp
-// GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 op_sel_hi:[0,0,0] clamp ; encoding: [0x00,0x80,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mixhi_f16 v0, v1, v2, v3 clamp ; encoding: [0x00,0x80,0xa2,0xd3,0x01,0x05,0x0e,0x04]
//
// op_sel with non-packed instructions
//
v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,0]
-// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0]
-// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x08,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x00,0x08,0xa0,0xd3,0x01,0x05,0x0e,0x04]
v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,1,0]
-// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,1,0] op_sel_hi:[0,0,0] ; encoding: [0x00,0x10,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,1,0] ; encoding: [0x00,0x10,0xa0,0xd3,0x01,0x05,0x0e,0x04]
v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,1]
-// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,1] op_sel_hi:[0,0,0] ; encoding: [0x00,0x20,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,1] ; encoding: [0x00,0x20,0xa0,0xd3,0x01,0x05,0x0e,0x04]
v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,1,1]
-// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,1,1] op_sel_hi:[0,0,0] ; encoding: [0x00,0x38,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,1,1] ; encoding: [0x00,0x38,0xa0,0xd3,0x01,0x05,0x0e,0x04]
v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0]
-// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,0,0]
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x0c]
@@ -252,7 +252,7 @@ v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[
// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[0,0,1] ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x04]
v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,1,1]
-// GFX9: v_mad_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+// GFX9: v_mad_mix_f32 v0, v1, v2, v3 op_sel_hi:[1,1,1] ; encoding: [0x00,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
v_mad_mixlo_f16 v0, v1, v2, v3 op_sel_hi:[1,0,1] clamp
// GFX9: v_mad_mixlo_f16 v0, v1, v2, v3 op_sel_hi:[1,0,1] clamp ; encoding: [0x00,0xc0,0xa1,0xd3,0x01,0x05,0x0e,0x0c]
Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt?rev=318526&r1=318525&r2=318526&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt Fri Nov 17 07:15:40 2017
@@ -188,3 +188,444 @@
# GFX9: v_mad_u16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x04,0xd2,0x01,0x05,0x0e,0x04]
0x05,0x80,0x04,0xd2,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v255, v1, v2, v3 ; encoding: [0xff,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0xff,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v255, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0xff,0x05,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0xff,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, s1, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x04,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0x04,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, s101, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x65,0x04,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x65,0x04,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, flat_scratch_lo, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x66,0x04,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x66,0x04,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, flat_scratch_hi, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x67,0x04,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x67,0x04,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, vcc_lo, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x6a,0x04,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x6a,0x04,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, vcc_hi, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x6b,0x04,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x6b,0x04,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, m0, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x7c,0x04,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x7c,0x04,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, exec_lo, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x7e,0x04,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x7e,0x04,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, exec_hi, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x7f,0x04,0x0e,0x04]
+0x05,0x00,0xa0,0xd3,0x7f,0x04,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v255, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xff,0x0f,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0xff,0x0f,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, s2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0c,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x0c,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, s101, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xcb,0x0c,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0xcb,0x0c,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, flat_scratch_lo, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xcd,0x0c,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0xcd,0x0c,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, flat_scratch_hi, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xcf,0x0c,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0xcf,0x0c,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, vcc_lo, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xd5,0x0c,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0xd5,0x0c,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, vcc_hi, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xd7,0x0c,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0xd7,0x0c,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, m0, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xf9,0x0c,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0xf9,0x0c,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, exec_lo, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xfd,0x0c,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0xfd,0x0c,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, exec_hi, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0xff,0x0c,0x04]
+0x05,0x00,0xa0,0xd3,0x01,0xff,0x0c,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v255 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x07]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x07
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x00]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x00
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, s101 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x96,0x01]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x96,0x01
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, flat_scratch_lo ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x9a,0x01]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x9a,0x01
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, flat_scratch_hi ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x9e,0x01]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x9e,0x01
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, vcc_lo ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xaa,0x01]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0xaa,0x01
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, vcc_hi ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xae,0x01]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0xae,0x01
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, m0 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xf2,0x01]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0xf2,0x01
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, exec_lo ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfa,0x01]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0xfa,0x01
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, exec_hi ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x01]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x01
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x05,0x08,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x08,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,1,0] ; encoding: [0x05,0x10,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x10,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,0,1] ; encoding: [0x05,0x20,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x20,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel:[1,1,1] ; encoding: [0x05,0x38,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x38,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x0c]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x0c
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,1,0] ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x14]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x14
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,0,1] ; encoding: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[1,1,1] ; encoding: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c
+
+# GFX9: v_mad_mix_f32 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x24]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x24
+
+# GFX9: v_mad_mix_f32 v5, v1, -v2, v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x44]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x44
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, -v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x84]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x84
+
+# GFX9: v_mad_mix_f32 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0xe4]
+0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0xe4
+
+# GFX9: v_mad_mix_f32 v5, |v1|, v2, v3 ; encoding: [0x05,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x07,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mix_f32 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xa0,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v255, v1, v2, v3 ; encoding: [0xff,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0xff,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v255, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0xff,0x05,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0xff,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, s1, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x04,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, s101, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x65,0x04,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x65,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, flat_scratch_lo, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x66,0x04,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x66,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, flat_scratch_hi, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x67,0x04,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x67,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, vcc_lo, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x6a,0x04,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x6a,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, vcc_hi, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x6b,0x04,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x6b,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, m0, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x7c,0x04,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x7c,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, exec_lo, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x7e,0x04,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x7e,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, exec_hi, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x7f,0x04,0x0e,0x04]
+0x05,0x00,0xa2,0xd3,0x7f,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v255, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xff,0x0f,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0xff,0x0f,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, s2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0c,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x0c,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, s101, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xcb,0x0c,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0xcb,0x0c,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, flat_scratch_lo, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xcd,0x0c,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0xcd,0x0c,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, flat_scratch_hi, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xcf,0x0c,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0xcf,0x0c,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, vcc_lo, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xd5,0x0c,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0xd5,0x0c,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, vcc_hi, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xd7,0x0c,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0xd7,0x0c,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, m0, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xf9,0x0c,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0xf9,0x0c,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, exec_lo, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xfd,0x0c,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0xfd,0x0c,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, exec_hi, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0xff,0x0c,0x04]
+0x05,0x00,0xa2,0xd3,0x01,0xff,0x0c,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v255 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xfe,0x07]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0xfe,0x07
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, s3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x00]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x00
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, s101 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x96,0x01]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x96,0x01
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, flat_scratch_lo ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x9a,0x01]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x9a,0x01
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, flat_scratch_hi ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x9e,0x01]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x9e,0x01
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, vcc_lo ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xaa,0x01]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0xaa,0x01
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, vcc_hi ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xae,0x01]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0xae,0x01
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, m0 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xf2,0x01]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0xf2,0x01
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, exec_lo ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xfa,0x01]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0xfa,0x01
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, exec_hi ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xfe,0x01]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0xfe,0x01
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x05,0x08,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x08,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[0,1,0] ; encoding: [0x05,0x10,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x10,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[0,0,1] ; encoding: [0x05,0x20,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x20,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[1,1,1] ; encoding: [0x05,0x38,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x38,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x0c]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x0c
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[0,1,0] ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x14]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x14
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[0,0,1] ; encoding: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[1,1,1] ; encoding: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
+0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x1c
+
+# GFX9: v_mad_mixhi_f16 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x24]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x24
+
+# GFX9: v_mad_mixhi_f16 v5, v1, -v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x44]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x44
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, -v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x84]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x84
+
+# GFX9: v_mad_mixhi_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0xe4]
+0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0xe4
+
+# GFX9: v_mad_mixhi_f16 v5, |v1|, v2, v3 ; encoding: [0x05,0x01,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x01,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x02,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x04,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x07,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xa2,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v255, v1, v2, v3 ; encoding: [0xff,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0xff,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v255, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0xff,0x05,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0xff,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, s1, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x04,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, s101, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x65,0x04,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x65,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, flat_scratch_lo, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x66,0x04,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x66,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, flat_scratch_hi, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x67,0x04,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x67,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, vcc_lo, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x6a,0x04,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x6a,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, vcc_hi, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x6b,0x04,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x6b,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, m0, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x7c,0x04,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x7c,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, exec_lo, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x7e,0x04,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x7e,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, exec_hi, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x7f,0x04,0x0e,0x04]
+0x05,0x00,0xa1,0xd3,0x7f,0x04,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v255, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xff,0x0f,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0xff,0x0f,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, s2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0c,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x0c,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, s101, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xcb,0x0c,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0xcb,0x0c,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, flat_scratch_lo, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xcd,0x0c,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0xcd,0x0c,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, flat_scratch_hi, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xcf,0x0c,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0xcf,0x0c,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, vcc_lo, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xd5,0x0c,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0xd5,0x0c,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, vcc_hi, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xd7,0x0c,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0xd7,0x0c,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, m0, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xf9,0x0c,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0xf9,0x0c,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, exec_lo, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xfd,0x0c,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0xfd,0x0c,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, exec_hi, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0xff,0x0c,0x04]
+0x05,0x00,0xa1,0xd3,0x01,0xff,0x0c,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v255 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xfe,0x07]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0xfe,0x07
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, s3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x00]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x00
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, s101 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x96,0x01]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x96,0x01
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, flat_scratch_lo ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x9a,0x01]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x9a,0x01
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, flat_scratch_hi ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x9e,0x01]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x9e,0x01
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, vcc_lo ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xaa,0x01]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0xaa,0x01
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, vcc_hi ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xae,0x01]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0xae,0x01
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, m0 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xf2,0x01]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0xf2,0x01
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, exec_lo ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xfa,0x01]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0xfa,0x01
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, exec_hi ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xfe,0x01]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0xfe,0x01
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x05,0x08,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x08,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[0,1,0] ; encoding: [0x05,0x10,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x10,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[0,0,1] ; encoding: [0x05,0x20,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x20,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[1,1,1] ; encoding: [0x05,0x38,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x38,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[1,0,0] ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x0c]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x0c
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[0,1,0] ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x14]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x14
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[0,0,1] ; encoding: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[1,1,1] ; encoding: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
+0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x1c
+
+# GFX9: v_mad_mixlo_f16 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x24]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x24
+
+# GFX9: v_mad_mixlo_f16 v5, v1, -v2, v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x44]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x44
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, -v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x84]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x84
+
+# GFX9: v_mad_mixlo_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0xe4]
+0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0xe4
+
+# GFX9: v_mad_mixlo_f16 v5, |v1|, v2, v3 ; encoding: [0x05,0x01,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x01,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x02,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x04,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x07,0xa1,0xd3,0x01,0x05,0x0e,0x04
+
+# GFX9: v_mad_mixlo_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04
More information about the llvm-commits
mailing list