[llvm] r318368 - [X86] Custom type legalize v2f32 masked gathers instead of trying to cleanup after type legalization.

[Craig Topper via llvm-commits]

Fixed in r318509.

~Craig

On Thu, Nov 16, 2017 at 11:04 PM, Akira Hatanaka via llvm-commits <
llvm-commits at lists.llvm.org> wrote:

> Can you revert this? This bot has been red since yesterday.
>
> On Thu, Nov 16, 2017 at 4:05 PM, Akira Hatanaka <ahatanak at gmail.com>
> wrote:
>
>> Do you know whether this is causing the following bot to fail?
>>
>> http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-
>> expensive/9317/consoleFull#1531177838d489585b-5106-414a-ac11-3ff90657619c
>>
>> The assertion in masked_gather_scatter.ll started to fail in build #9307.
>>
>> On Wed, Nov 15, 2017 at 6:07 PM, Craig Topper via llvm-commits <
>> llvm-commits at lists.llvm.org> wrote:
>>
>>> Author: ctopper
>>> Date: Wed Nov 15 18:07:45 2017
>>> New Revision: 318368
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=318368&view=rev
>>> Log:
>>> [X86] Custom type legalize v2f32 masked gathers instead of trying to
>>> cleanup after type legalization.
>>>
>>> Modified:
>>>     llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>>>
>>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X8
>>> 6/X86ISelLowering.cpp?rev=318368&r1=318367&r2=318368&view=diff
>>> ============================================================
>>> ==================
>>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
>>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Nov 15 18:07:45
>>> 2017
>>> @@ -1370,6 +1370,11 @@ X86TargetLowering::X86TargetLowering(con
>>>          setOperationAction(ISD::CTPOP, VT, Legal);
>>>      }
>>>
>>> +    // Custom legalize 2x32 to get a little better code.
>>> +    if (Subtarget.hasVLX()) {
>>> +      setOperationAction(ISD::MGATHER, MVT::v2f32, Custom);
>>> +    }
>>> +
>>>      // Custom lower several nodes.
>>>      for (auto VT : { MVT::v4i32, MVT::v8i32, MVT::v2i64, MVT::v4i64,
>>>                       MVT::v4f32, MVT::v8f32, MVT::v2f64, MVT::v4f64 }) {
>>> @@ -24378,32 +24383,6 @@ static SDValue LowerMGATHER(SDValue Op,
>>>      SDValue RetOps[] = { Sext, NewGather.getValue(1) };
>>>      return DAG.getMergeValues(RetOps, dl);
>>>    }
>>> -  if (N->getMemoryVT() == MVT::v2f32 && Subtarget.hasVLX()) {
>>> -    // This transformation is for optimization only.
>>> -    // The type legalizer extended mask and index to 4 elements vector
>>> -    // in order to match requirements of the common gather node - same
>>> -    // vector width of index and value. X86 Gather node allows mismatch
>>> -    // of vector width in order to select more optimal instruction at
>>> the
>>> -    // end.
>>> -    assert(VT == MVT::v4f32 && Src0.getValueType() == MVT::v4f32 &&
>>> -           "Unexpected type in masked gather");
>>> -    if (Mask.getOpcode() == ISD::CONCAT_VECTORS &&
>>> -        ISD::isBuildVectorAllZeros(Mask.getOperand(1).getNode()) &&
>>> -        Index.getOpcode() == ISD::CONCAT_VECTORS &&
>>> -        Index.getOperand(1).isUndef()) {
>>> -      Mask = Mask.getOperand(0);
>>> -      Index = Index.getOperand(0);
>>> -    } else
>>> -      return Op;
>>> -    SDValue Ops[] = { N->getChain(), Src0, Mask, N->getBasePtr(), Index
>>> };
>>> -    SDValue NewGather = DAG.getTargetMemSDNode<X86MaskedGatherSDNode>(
>>> -      DAG.getVTList(MVT::v4f32, MVT::v2i1, MVT::Other), Ops, dl,
>>> -      N->getMemoryVT(), N->getMemOperand());
>>> -
>>> -    SDValue RetOps[] = { NewGather.getValue(0), NewGather.getValue(2) };
>>> -    return DAG.getMergeValues(RetOps, dl);
>>> -
>>> -  }
>>>    return Op;
>>>  }
>>>
>>> @@ -24902,6 +24881,29 @@ void X86TargetLowering::ReplaceNodeResul
>>>      Results.push_back(DAG.getBuildVector(DstVT, dl, Elts));
>>>      return;
>>>    }
>>> +  case ISD::MGATHER: {
>>> +    EVT VT = N->getValueType(0);
>>> +    if (VT == MVT::v2f32 && Subtarget.hasVLX()) {
>>> +      auto *Gather = cast<MaskedGatherSDNode>(N);
>>> +      SDValue Index = Gather->getIndex();
>>> +      if (Index.getValueType() != MVT::v2i64)
>>> +        return;
>>> +      SDValue Mask = Gather->getMask();
>>> +      assert(Mask.getValueType() == MVT::v2i1 && "Unexpected mask
>>> type");
>>> +      SDValue Src0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
>>> +                                 Gather->getValue(),
>>> +                                 DAG.getUNDEF(MVT::v2f32));
>>> +      SDValue Ops[] = { Gather->getChain(), Src0, Mask,
>>> Gather->getBasePtr(),
>>> +                        Index };
>>> +      SDValue Res = DAG.getTargetMemSDNode<X86MaskedGatherSDNode>(
>>> +        DAG.getVTList(MVT::v4f32, MVT::v2i1, MVT::Other), Ops, dl,
>>> +        Gather->getMemoryVT(), Gather->getMemOperand());
>>> +      Results.push_back(Res);
>>> +      Results.push_back(Res.getValue(2));
>>> +      return;
>>> +    }
>>> +    break;
>>> +  }
>>>    }
>>>  }
>>>
>>>
>>>
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