[PATCH] D40155: AMDGPU: Fix breaking SMEM clauses

[Tony Tye via Phabricator via llvm-commits]

t-tye added inline comments.


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Comment at: lib/Target/AMDGPU/GCNHazardRecognizer.cpp:280
+void GCNHazardRecognizer::addClauseInst(const MachineInstr &MI) {
+  // XXX: Do we need to worry about implicit operands
+  addRegsToSet(TRI, MI.defs(), ClauseDefs);
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Can implicit operands be registers? Is the only such case M0 which can never be modified. So probably not?


https://reviews.llvm.org/D40155