[PATCH] D39895: [RISCV] MC layer support for the standard RV32D instruction set extension

[Ana Pazos via Phabricator via llvm-commits]

apazos added inline comments.


================
Comment at: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:427
+  RISCVOperand &Op = static_cast<RISCVOperand &>(AsmOp);
+  if (Op.isReg()) {
+    unsigned Reg = Op.getReg();
----------------
consider early exit, return  Match_InvalidOperand from here if Op not Reg


================
Comment at: lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp:124
+                                             const void *Decoder) {
+  if (RegNo > sizeof(FPR64DecoderTable)) {
+    return MCDisassembler::Fail;
----------------
extra {}


https://reviews.llvm.org/D39895