[PATCH] D40148: [AMDGPU] Fix SITargetLowering::lowerEXTRACT_VECTOR_ELT for constant type

[Yaxun Liu via Phabricator via llvm-commits]

yaxunl created this revision.
Herald added subscribers: t-tye, tpr, dstuttard, nhaehnle, wdng, kzhuravl.

When doing isel for the lit test with new address space mapping,
 two SDNode for constant 16 is generated:

t52: i32 = srl t44, Constant:i64<16> is generated by SplitVecRes_BITCAS
 when legalizing t37: v2i16 = bitcast t44, which in turn calls SplitInteger,
 where default pointer type is used for the constant 16.

t60: i32 = srl t44, Constant:i32<16> is generated by
SITargetLowering::lowerEXTRACT_VECTOR_ELT when
legalizing t56: i32 = extract_vector_elt t37, Constant:i32<1>,
where i32 is used for the constant 16.

With the old address space mapping, there is only one SDNode for `srl t44, 16`
since in the old address space mapping default pointer is 32 bit.

This results in longer and slower ISA with amdgiz, and causes
regression in the lit test.

This patch fixes that by using the default pointer type for constant 16
in SITargetLowering::lowerEXTRACT_VECTOR_ELT


https://reviews.llvm.org/D40148

Files:
  lib/Target/AMDGPU/SIISelLowering.cpp
  test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll


Index: test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
===================================================================
--- test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
+++ test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
@@ -1,6 +1,6 @@
-; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=gfx901 -enable-amdgpu-aa=0 -mattr=+flat-for-global,-fp64-fp16-denormals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s
-; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=fiji -enable-amdgpu-aa=0 -mattr=+flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=CIVI -check-prefix=VI -check-prefix=GFX89 %s
-; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=hawaii -enable-amdgpu-aa=0 -mattr=+flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=CIVI -check-prefix=CI %s
+; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx901 -enable-amdgpu-aa=0 -mattr=+flat-for-global,-fp64-fp16-denormals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s
+; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -enable-amdgpu-aa=0 -mattr=+flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=CIVI -check-prefix=VI -check-prefix=GFX89 %s
+; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=hawaii -enable-amdgpu-aa=0 -mattr=+flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=CIVI -check-prefix=CI %s
 
 ; GCN-LABEL: {{^}}s_insertelement_v2i16_0:
 ; GCN: s_load_dword [[VEC:s[0-9]+]]
Index: lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- lib/Target/AMDGPU/SIISelLowering.cpp
+++ lib/Target/AMDGPU/SIISelLowering.cpp
@@ -3699,7 +3699,7 @@
 
     if (CIdx->getZExtValue() == 1) {
       Result = DAG.getNode(ISD::SRL, SL, MVT::i32, Result,
-                           DAG.getConstant(16, SL, MVT::i32));
+                           DAG.getIntPtrConstant(16, SL));
     } else {
       assert(CIdx->getZExtValue() == 0);
     }
@@ -3709,7 +3709,7 @@
     return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);
   }
 
-  SDValue Sixteen = DAG.getConstant(16, SL, MVT::i32);
+  SDValue Sixteen = DAG.getIntPtrConstant(16, SL);
 
   // Convert vector index to bit-index.
   SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, Sixteen);


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