[PATCH] D40124: A new sched model for SHLD/SHRD, MOV and RET on btver2

[Andrew V. Tischenko via Phabricator via llvm-commits]

avt77 created this revision.

This patch is the first step to implement proper usage of SHLD/SHRD on Machine Combiner level. First of all the patch introduces proper sched model for these 2 instructions. Secondly, the patch adds new schedule test specially for SHLD/SHRD. And finaly, the patch fixes modeling of MOV and RET instructions on btver2: now we have valid [latency:throughput] numbers for them. As result many existing tests were updated to mirror this last change.

In the next patch I'm going to introduce the selection of the best code sequence (SHLD/SHRD or alternative) based on [latency:throughput] numbers.


https://reviews.llvm.org/D40124

Files:
  lib/Target/X86/X86ScheduleBtVer2.td
  test/CodeGen/X86/aes-schedule.ll
  test/CodeGen/X86/avx-schedule.ll
  test/CodeGen/X86/bmi-schedule.ll
  test/CodeGen/X86/f16c-schedule.ll
  test/CodeGen/X86/lea32-schedule.ll
  test/CodeGen/X86/lea64-schedule.ll
  test/CodeGen/X86/lzcnt-schedule.ll
  test/CodeGen/X86/mmx-schedule.ll
  test/CodeGen/X86/movbe-schedule.ll
  test/CodeGen/X86/mul-constant-i32.ll
  test/CodeGen/X86/mul-constant-i64.ll
  test/CodeGen/X86/popcnt-schedule.ll
  test/CodeGen/X86/recip-fastmath.ll
  test/CodeGen/X86/recip-fastmath2.ll
  test/CodeGen/X86/schedule-x86-64-shld.ll
  test/CodeGen/X86/schedule-x86_32.ll
  test/CodeGen/X86/schedule-x86_64.ll
  test/CodeGen/X86/sse-schedule.ll
  test/CodeGen/X86/sse2-schedule.ll
  test/CodeGen/X86/sse3-schedule.ll
  test/CodeGen/X86/sse41-schedule.ll
  test/CodeGen/X86/sse42-schedule.ll
  test/CodeGen/X86/sse4a-schedule.ll
  test/CodeGen/X86/ssse3-schedule.ll

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