[llvm] r318393 - [ARM GlobalISel] Add tests for REVSH patterns. NFC
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 16 04:29:28 PST 2017
Author: rovka
Date: Thu Nov 16 04:29:28 2017
New Revision: 318393
URL: http://llvm.org/viewvc/llvm-project?rev=318393&view=rev
Log:
[ARM GlobalISel] Add tests for REVSH patterns. NFC
Add instruction selector tests for some of the REVSH patterns handled by
TableGen.
Modified:
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir?rev=318393&r1=318392&r2=318393&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir Thu Nov 16 04:29:28 2017
@@ -7,6 +7,11 @@
define void @test_mls() #2 { ret void }
define void @test_no_mls() { ret void }
+ define void @test_shifts_to_revsh() #0 { ret void }
+ define void @test_shifts_to_revsh_commutative() #0 { ret void }
+ define void @test_shifts_no_revsh_features() #1 { ret void }
+ define void @test_shifts_no_revsh_constants() #0 { ret void }
+
attributes #0 = { "target-features"="+v6" }
attributes #1 = { "target-features"="-v6" }
attributes #2 = { "target-features"="+v6t2" }
@@ -182,3 +187,183 @@ body: |
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
+---
+name: test_shifts_to_revsh
+# CHECK-LABEL: name: test_shifts_to_revsh
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+ - { id: 4, class: gprb }
+ - { id: 5, class: gprb }
+ - { id: 6, class: gprb }
+ - { id: 7, class: gprb }
+ - { id: 8, class: gprb }
+ - { id: 9, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(s32) = COPY %r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+
+ %1(s32) = G_CONSTANT i32 24
+ %2(s32) = G_SHL %0(s32), %1(s32)
+
+ %3(s32) = G_CONSTANT i32 16
+ %4(s32) = G_ASHR %2(s32), %3(s32)
+
+ %5(s32) = G_CONSTANT i32 8
+ %6(s32) = G_LSHR %0(s32), %5(s32)
+
+ %7(s32) = G_CONSTANT 255
+ %8(s32) = G_AND %6(s32), %7(s32)
+
+ %9(s32) = G_OR %4(s32), %8(s32)
+ ; CHECK: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
+
+ %r0 = COPY %9(s32)
+ ; CHECK: %r0 = COPY [[VREGR]]
+
+ BX_RET 14, _, implicit %r0
+ ; CHECK: BX_RET 14, _, implicit %r0
+...
+---
+name: test_shifts_to_revsh_commutative
+# CHECK-LABEL: name: test_shifts_to_revsh_commutative
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+ - { id: 4, class: gprb }
+ - { id: 5, class: gprb }
+ - { id: 6, class: gprb }
+ - { id: 7, class: gprb }
+ - { id: 8, class: gprb }
+ - { id: 9, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(s32) = COPY %r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+
+ %1(s32) = G_CONSTANT i32 24
+ %2(s32) = G_SHL %0(s32), %1(s32)
+
+ %3(s32) = G_CONSTANT i32 16
+ %4(s32) = G_ASHR %2(s32), %3(s32)
+
+ %5(s32) = G_CONSTANT i32 8
+ %6(s32) = G_LSHR %0(s32), %5(s32)
+
+ %7(s32) = G_CONSTANT 255
+ %8(s32) = G_AND %6(s32), %7(s32)
+
+ %9(s32) = G_OR %8(s32), %4(s32)
+ ; CHECK: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
+
+ %r0 = COPY %9(s32)
+ ; CHECK: %r0 = COPY [[VREGR]]
+
+ BX_RET 14, _, implicit %r0
+ ; CHECK: BX_RET 14, _, implicit %r0
+...
+---
+name: test_shifts_no_revsh_features
+# CHECK-LABEL: name: test_shifts_no_revsh
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+ - { id: 4, class: gprb }
+ - { id: 5, class: gprb }
+ - { id: 6, class: gprb }
+ - { id: 7, class: gprb }
+ - { id: 8, class: gprb }
+ - { id: 9, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(s32) = COPY %r0
+
+ %1(s32) = G_CONSTANT i32 24
+ %2(s32) = G_SHL %0(s32), %1(s32)
+
+ %3(s32) = G_CONSTANT i32 16
+ %4(s32) = G_ASHR %2(s32), %3(s32)
+
+ %5(s32) = G_CONSTANT i32 8
+ %6(s32) = G_LSHR %0(s32), %5(s32)
+
+ %7(s32) = G_CONSTANT 255
+ %8(s32) = G_AND %6(s32), %7(s32)
+
+ %9(s32) = G_OR %4(s32), %8(s32)
+ ; We don't really care how this is folded as long as it's not into a REVSH.
+ ; CHECK-NOT: REVSH
+
+ %r0 = COPY %9(s32)
+
+ BX_RET 14, _, implicit %r0
+...
+---
+name: test_shifts_no_revsh_constants
+# CHECK-LABEL: name: test_shifts_no_revsh_constants
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+ - { id: 4, class: gprb }
+ - { id: 5, class: gprb }
+ - { id: 6, class: gprb }
+ - { id: 7, class: gprb }
+ - { id: 8, class: gprb }
+ - { id: 9, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(s32) = COPY %r0
+
+ %1(s32) = G_CONSTANT i32 16 ; REVSH needs 24 here
+ %2(s32) = G_SHL %0(s32), %1(s32)
+
+ %3(s32) = G_CONSTANT i32 24 ; REVSH needs 16 here
+ %4(s32) = G_ASHR %2(s32), %3(s32)
+
+ %5(s32) = G_CONSTANT i32 8
+ %6(s32) = G_LSHR %0(s32), %5(s32)
+
+ %7(s32) = G_CONSTANT 255
+ %8(s32) = G_AND %6(s32), %7(s32)
+
+ %9(s32) = G_OR %4(s32), %8(s32)
+ ; We don't really care how this is folded as long as it's not into a REVSH.
+ ; CHECK-NOT: REVSH
+
+ %r0 = COPY %9(s32)
+
+ BX_RET 14, _, implicit %r0
+...
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