[llvm] r318351 - [AArch64] Adjust the cost model for Exynos M1 and M2
Evandro Menezes via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 15 15:49:58 PST 2017
Author: evandro
Date: Wed Nov 15 15:49:58 2017
New Revision: 318351
URL: http://llvm.org/viewvc/llvm-project?rev=318351&view=rev
Log:
[AArch64] Adjust the cost model for Exynos M1 and M2
Fix the modeling of FP stores.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td?rev=318351&r1=318350&r2=318351&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td Wed Nov 15 15:49:58 2017
@@ -111,15 +111,18 @@ def M1WriteS4 : SchedWriteRes<[M1UnitS]>
def M1WriteSA : SchedWriteRes<[M1UnitS,
M1UnitFST,
M1UnitS,
- M1UnitFST]> { let Latency = 1; }
+ M1UnitFST]> { let Latency = 1;
+ let NumMicroOps = 2; }
def M1WriteSB : SchedWriteRes<[M1UnitS,
M1UnitFST,
- M1UnitA]> { let Latency = 2; }
+ M1UnitA]> { let Latency = 2;
+ let NumMicroOps = 2; }
def M1WriteSC : SchedWriteRes<[M1UnitS,
M1UnitFST,
M1UnitS,
M1UnitFST,
- M1UnitA]> { let Latency = 1; }
+ M1UnitA]> { let Latency = 3;
+ let NumMicroOps = 3; }
def M1WriteSX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteS1]>,
SchedVar<NoSchedPred, [M1WriteA1,
M1WriteS1]>]>;
@@ -193,7 +196,8 @@ def : WriteRes<WriteVLD, [M1UnitL]> {
// FP store instructions.
def : WriteRes<WriteVST, [M1UnitS,
- M1UnitFST]> { let Latency = 1; }
+ M1UnitFST]> { let Latency = 1;
+ let NumMicroOps = 1; }
// ASIMD FP instructions.
def : WriteRes<WriteV, [M1UnitFADD]> { let Latency = 3; }
@@ -335,12 +339,14 @@ def M1WriteVSTC : WriteSequence<[Writ
def M1WriteVSTD : SchedWriteRes<[M1UnitS,
M1UnitFST,
M1UnitFST]> { let Latency = 7;
+ let NumMicroOps = 2;
let ResourceCycles = [7]; }
def M1WriteVSTE : SchedWriteRes<[M1UnitS,
M1UnitFST,
M1UnitS,
M1UnitFST,
M1UnitFST]> { let Latency = 8;
+ let NumMicroOps = 3;
let ResourceCycles = [8]; }
def M1WriteVSTF : SchedWriteRes<[M1UnitNALU,
M1UnitS,
@@ -349,6 +355,7 @@ def M1WriteVSTF : SchedWriteRes<[M1Un
M1UnitFST,
M1UnitFST,
M1UnitFST]> { let Latency = 15;
+ let NumMicroOps = 5;
let ResourceCycles = [15]; }
def M1WriteVSTG : SchedWriteRes<[M1UnitNALU,
M1UnitS,
@@ -359,12 +366,14 @@ def M1WriteVSTG : SchedWriteRes<[M1Un
M1UnitFST,
M1UnitFST,
M1UnitFST]> { let Latency = 16;
+ let NumMicroOps = 6;
let ResourceCycles = [16]; }
def M1WriteVSTH : SchedWriteRes<[M1UnitNALU,
M1UnitS,
M1UnitFST,
M1UnitFST,
M1UnitFST]> { let Latency = 14;
+ let NumMicroOps = 4;
let ResourceCycles = [14]; }
def M1WriteVSTI : SchedWriteRes<[M1UnitNALU,
M1UnitS,
@@ -377,6 +386,7 @@ def M1WriteVSTI : SchedWriteRes<[M1Un
M1UnitFST,
M1UnitFST,
M1UnitFST]> { let Latency = 17;
+ let NumMicroOps = 7;
let ResourceCycles = [17]; }
// Branch instructions
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