[llvm] r318308 - [X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule class
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 15 09:11:24 PST 2017
Author: rksimon
Date: Wed Nov 15 09:11:24 2017
New Revision: 318308
URL: http://llvm.org/viewvc/llvm-project?rev=318308&view=rev
Log:
[X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule class
Some CPUs are already overriding these sign extension instructions but we should be able to use the WriteALU schedule class by default.
Differential Revision: https://reviews.llvm.org/D39899
Modified:
llvm/trunk/lib/Target/X86/X86InstrExtension.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrExtension.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrExtension.td?rev=318308&r1=318307&r2=318308&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrExtension.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrExtension.td Wed Nov 15 09:11:24 2017
@@ -9,38 +9,36 @@
//
// This file describes the sign and zero extension operations.
//
-//===----------------------------------------------------------------------===//
-
-let hasSideEffects = 0 in {
- let Defs = [AX], Uses = [AL] in
- def CBW : I<0x98, RawFrm, (outs), (ins),
- "{cbtw|cbw}", [], IIC_CBW>, OpSize16; // AX = signext(AL)
- let Defs = [EAX], Uses = [AX] in
- def CWDE : I<0x98, RawFrm, (outs), (ins),
- "{cwtl|cwde}", [], IIC_CBW>, OpSize32; // EAX = signext(AX)
-
- let Defs = [AX,DX], Uses = [AX] in
- def CWD : I<0x99, RawFrm, (outs), (ins),
- "{cwtd|cwd}", [], IIC_CBW>, OpSize16; // DX:AX = signext(AX)
- let Defs = [EAX,EDX], Uses = [EAX] in
- def CDQ : I<0x99, RawFrm, (outs), (ins),
- "{cltd|cdq}", [], IIC_CBW>, OpSize32; // EDX:EAX = signext(EAX)
-
-
- let Defs = [RAX], Uses = [EAX] in
- def CDQE : RI<0x98, RawFrm, (outs), (ins),
- "{cltq|cdqe}", [], IIC_CBW>; // RAX = signext(EAX)
-
- let Defs = [RAX,RDX], Uses = [RAX] in
- def CQO : RI<0x99, RawFrm, (outs), (ins),
- "{cqto|cqo}", [], IIC_CBW>; // RDX:RAX = signext(RAX)
-}
-
-
-
-// Sign/Zero extenders
-let hasSideEffects = 0 in {
-def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0 in {
+ let Defs = [AX], Uses = [AL] in // AX = signext(AL)
+ def CBW : I<0x98, RawFrm, (outs), (ins),
+ "{cbtw|cbw}", [], IIC_CBW>, OpSize16, Sched<[WriteALU]>;
+ let Defs = [EAX], Uses = [AX] in // EAX = signext(AX)
+ def CWDE : I<0x98, RawFrm, (outs), (ins),
+ "{cwtl|cwde}", [], IIC_CBW>, OpSize32, Sched<[WriteALU]>;
+
+ let Defs = [AX,DX], Uses = [AX] in // DX:AX = signext(AX)
+ def CWD : I<0x99, RawFrm, (outs), (ins),
+ "{cwtd|cwd}", [], IIC_CBW>, OpSize16, Sched<[WriteALU]>;
+ let Defs = [EAX,EDX], Uses = [EAX] in // EDX:EAX = signext(EAX)
+ def CDQ : I<0x99, RawFrm, (outs), (ins),
+ "{cltd|cdq}", [], IIC_CBW>, OpSize32, Sched<[WriteALU]>;
+
+
+ let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX)
+ def CDQE : RI<0x98, RawFrm, (outs), (ins),
+ "{cltq|cdqe}", [], IIC_CBW>, Sched<[WriteALU]>;
+
+ let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX)
+ def CQO : RI<0x99, RawFrm, (outs), (ins),
+ "{cqto|cqo}", [], IIC_CBW>, Sched<[WriteALU]>;
+}
+
+// Sign/Zero extenders
+let hasSideEffects = 0 in {
+def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
"movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_R8>,
TB, OpSize16, Sched<[WriteALU]>;
let mayLoad = 1 in
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=318308&r1=318307&r2=318308&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Wed Nov 15 09:11:24 2017
@@ -865,6 +865,7 @@ def SBWriteResGroup15 : SchedWriteRes<[S
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
+def: InstRW<[SBWriteResGroup15], (instregex "CWD")>;
def: InstRW<[SBWriteResGroup15], (instregex "FNSTSW16r")>;
def SBWriteResGroup16 : SchedWriteRes<[SBPort1,SBPort05]> {
Modified: llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll?rev=318308&r1=318307&r2=318308&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll Wed Nov 15 09:11:24 2017
@@ -755,7 +755,7 @@ define void @test_cbw_cdq_cdqe_cqo_cwd_c
; GENERIC-NEXT: cltd # sched: [1:0.50]
; GENERIC-NEXT: cltq # sched: [1:0.50]
; GENERIC-NEXT: cqto # sched: [1:0.50]
-; GENERIC-NEXT: cwtd
+; GENERIC-NEXT: cwtd # sched: [2:1.00]
; GENERIC-NEXT: cwtl # sched: [1:0.33]
; GENERIC-NEXT: #NO_APP
; GENERIC-NEXT: retq # sched: [1:1.00]
@@ -775,12 +775,12 @@ define void @test_cbw_cdq_cdqe_cqo_cwd_c
; SLM-LABEL: test_cbw_cdq_cdqe_cqo_cwd_cwde:
; SLM: # BB#0:
; SLM-NEXT: #APP
-; SLM-NEXT: cbtw
-; SLM-NEXT: cltd
-; SLM-NEXT: cltq
-; SLM-NEXT: cqto
-; SLM-NEXT: cwtd
-; SLM-NEXT: cwtl
+; SLM-NEXT: cbtw # sched: [1:0.50]
+; SLM-NEXT: cltd # sched: [1:0.50]
+; SLM-NEXT: cltq # sched: [1:0.50]
+; SLM-NEXT: cqto # sched: [1:0.50]
+; SLM-NEXT: cwtd # sched: [1:0.50]
+; SLM-NEXT: cwtl # sched: [1:0.50]
; SLM-NEXT: #NO_APP
; SLM-NEXT: retq # sched: [4:1.00]
;
@@ -791,7 +791,7 @@ define void @test_cbw_cdq_cdqe_cqo_cwd_c
; SANDY-NEXT: cltd # sched: [1:0.50]
; SANDY-NEXT: cltq # sched: [1:0.50]
; SANDY-NEXT: cqto # sched: [1:0.50]
-; SANDY-NEXT: cwtd
+; SANDY-NEXT: cwtd # sched: [2:1.00]
; SANDY-NEXT: cwtl # sched: [1:0.33]
; SANDY-NEXT: #NO_APP
; SANDY-NEXT: retq # sched: [1:1.00]
@@ -847,24 +847,24 @@ define void @test_cbw_cdq_cdqe_cqo_cwd_c
; BTVER2-LABEL: test_cbw_cdq_cdqe_cqo_cwd_cwde:
; BTVER2: # BB#0:
; BTVER2-NEXT: #APP
-; BTVER2-NEXT: cbtw
-; BTVER2-NEXT: cltd
-; BTVER2-NEXT: cltq
-; BTVER2-NEXT: cqto
-; BTVER2-NEXT: cwtd
-; BTVER2-NEXT: cwtl
+; BTVER2-NEXT: cbtw # sched: [1:0.50]
+; BTVER2-NEXT: cltd # sched: [1:0.50]
+; BTVER2-NEXT: cltq # sched: [1:0.50]
+; BTVER2-NEXT: cqto # sched: [1:0.50]
+; BTVER2-NEXT: cwtd # sched: [1:0.50]
+; BTVER2-NEXT: cwtl # sched: [1:0.50]
; BTVER2-NEXT: #NO_APP
; BTVER2-NEXT: retq # sched: [4:1.00]
;
; ZNVER1-LABEL: test_cbw_cdq_cdqe_cqo_cwd_cwde:
; ZNVER1: # BB#0:
; ZNVER1-NEXT: #APP
-; ZNVER1-NEXT: cbtw
-; ZNVER1-NEXT: cltd
-; ZNVER1-NEXT: cltq
-; ZNVER1-NEXT: cqto
-; ZNVER1-NEXT: cwtd
-; ZNVER1-NEXT: cwtl
+; ZNVER1-NEXT: cbtw # sched: [1:0.25]
+; ZNVER1-NEXT: cltd # sched: [1:0.25]
+; ZNVER1-NEXT: cltq # sched: [1:0.25]
+; ZNVER1-NEXT: cqto # sched: [1:0.25]
+; ZNVER1-NEXT: cwtd # sched: [1:0.25]
+; ZNVER1-NEXT: cwtl # sched: [1:0.25]
; ZNVER1-NEXT: #NO_APP
; ZNVER1-NEXT: retq # sched: [1:0.50]
tail call void asm "cbw \0A\09 cdq \0A\09 cdqe \0A\09 cqo \0A\09 cwd \0A\09 cwde", ""() nounwind
More information about the llvm-commits
mailing list