[llvm] r318210 - [GISel]: Rework legalization algorithm for better elimination of
Aditya Nandakumar via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 14 14:42:19 PST 2017
Author: aditya_nandakumar
Date: Tue Nov 14 14:42:19 2017
New Revision: 318210
URL: http://llvm.org/viewvc/llvm-project?rev=318210&view=rev
Log:
[GISel]: Rework legalization algorithm for better elimination of
artifacts along with DCE
Legalization Artifacts are all those insts that are there to make the
type system happy. Currently, the target needs to say all combinations
of extends and truncs are legal and there's no way of verifying that
post legalization, we only have *truly* legal instructions. This patch
changes roughly the legalization algorithm to process all illegal insts
at one go, and then process all truncs/extends that were added to
satisfy the type constraints separately trying to combine trivial cases
until they converge. This has the added benefit that, the target
legalizerinfo can only say which truncs and extends are okay and the
artifact combiner would combine away other exts and truncs.
Updated legalization algorithm to roughly the following pseudo code.
WorkList Insts, Artifacts;
collect_all_insts_and_artifacts(Insts, Artifacts);
do {
for (Inst in Insts)
legalizeInstrStep(Inst, Insts, Artifacts);
for (Artifact in Artifacts)
tryCombineArtifact(Artifact, Insts, Artifacts);
} while(!Insts.empty());
Also, wrote a simple wrapper equivalent to SetVector, except for
erasing, it avoids moving all elements over by one and instead just
nulls them out.
Added:
llvm/trunk/include/llvm/CodeGen/GlobalISel/GISelWorkList.h
llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
- copied, changed from r318070, llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerCombiner.h
Removed:
llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerCombiner.h
Modified:
llvm/trunk/lib/CodeGen/GlobalISel/Legalizer.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/add-scalar.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/and-scalar.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/ext.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add-v128.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-constant.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-ext.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-gep.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-memop-scalar.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-phi.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-trunc.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-undef.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/or-scalar.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/sub-scalar.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-fallback.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/xor-scalar.ll
Added: llvm/trunk/include/llvm/CodeGen/GlobalISel/GISelWorkList.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/GISelWorkList.h?rev=318210&view=auto
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/GISelWorkList.h (added)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/GISelWorkList.h Tue Nov 14 14:42:19 2017
@@ -0,0 +1,67 @@
+//===- GISelWorkList.h - Worklist for GISel passes ----*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_GISEL_WORKLIST_H
+#define LLVM_GISEL_WORKLIST_H
+
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/Support/Debug.h"
+
+namespace llvm {
+
+// Worklist which mostly works similar to InstCombineWorkList, but on MachineInstrs.
+// The main difference with something like a SetVector is that erasing an element doesn't
+// move all elements over one place - instead just nulls out the element of the vector.
+// FIXME: Does it make sense to factor out common code with the instcombinerWorkList?
+template<unsigned N>
+class GISelWorkList {
+ SmallVector<MachineInstr*, N> Worklist;
+ DenseMap<MachineInstr*, unsigned> WorklistMap;
+
+public:
+ GISelWorkList() = default;
+
+ bool empty() const { return WorklistMap.empty(); }
+
+ unsigned size() const { return WorklistMap.size(); }
+
+ /// Add - Add the specified instruction to the worklist if it isn't already
+ /// in it.
+ void insert(MachineInstr *I) {
+ if (WorklistMap.try_emplace(I, Worklist.size()).second) {
+ Worklist.push_back(I);
+ }
+ }
+
+ /// Remove - remove I from the worklist if it exists.
+ void remove(MachineInstr *I) {
+ auto It = WorklistMap.find(I);
+ if (It == WorklistMap.end()) return; // Not in worklist.
+
+ // Don't bother moving everything down, just null out the slot.
+ Worklist[It->second] = nullptr;
+
+ WorklistMap.erase(It);
+ }
+
+ MachineInstr *pop_back_val() {
+ MachineInstr *I;
+ do {
+ I = Worklist.pop_back_val();
+ } while(!I);
+ assert(I && "Pop back on empty worklist");
+ WorklistMap.erase(I);
+ return I;
+ }
+};
+
+} // end namespace llvm.
+
+#endif
Copied: llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h (from r318070, llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerCombiner.h)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h?p2=llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h&p1=llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerCombiner.h&r1=318070&r2=318210&rev=318210&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerCombiner.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h Tue Nov 14 14:42:19 2017
@@ -1,4 +1,4 @@
-//===-- llvm/CodeGen/GlobalISel/LegalizerCombiner.h --===========//
+//===-- llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h --===========//
//
// The LLVM Compiler Infrastructure
//
@@ -22,13 +22,13 @@
#define DEBUG_TYPE "legalizer"
namespace llvm {
-class LegalizerCombiner {
+class LegalizationArtifactCombiner {
MachineIRBuilder &Builder;
MachineRegisterInfo &MRI;
const LegalizerInfo &LI;
public:
- LegalizerCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI,
+ LegalizationArtifactCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI,
const LegalizerInfo &LI)
: Builder(B), MRI(MRI), LI(LI) {}
@@ -36,8 +36,8 @@ public:
SmallVectorImpl<MachineInstr *> &DeadInsts) {
if (MI.getOpcode() != TargetOpcode::G_ANYEXT)
return false;
- MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(1).getReg());
- if (DefMI->getOpcode() == TargetOpcode::G_TRUNC) {
+ if (MachineInstr *DefMI =
+ getOpcodeDef(TargetOpcode::G_TRUNC, MI.getOperand(1).getReg())) {
DEBUG(dbgs() << ".. Combine MI: " << MI;);
unsigned DstReg = MI.getOperand(0).getReg();
unsigned SrcReg = DefMI->getOperand(1).getReg();
@@ -47,7 +47,7 @@ public:
markInstAndDefDead(MI, *DefMI, DeadInsts);
return true;
}
- return false;
+ return tryFoldImplicitDef(MI, DeadInsts);
}
bool tryCombineZExt(MachineInstr &MI,
@@ -55,8 +55,8 @@ public:
if (MI.getOpcode() != TargetOpcode::G_ZEXT)
return false;
- MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(1).getReg());
- if (DefMI->getOpcode() == TargetOpcode::G_TRUNC) {
+ if (MachineInstr *DefMI =
+ getOpcodeDef(TargetOpcode::G_TRUNC, MI.getOperand(1).getReg())) {
unsigned DstReg = MI.getOperand(0).getReg();
LLT DstTy = MRI.getType(DstReg);
if (isInstUnsupported(TargetOpcode::G_AND, DstTy) ||
@@ -75,7 +75,7 @@ public:
markInstAndDefDead(MI, *DefMI, DeadInsts);
return true;
}
- return false;
+ return tryFoldImplicitDef(MI, DeadInsts);
}
bool tryCombineSExt(MachineInstr &MI,
@@ -83,8 +83,8 @@ public:
if (MI.getOpcode() != TargetOpcode::G_SEXT)
return false;
- MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(1).getReg());
- if (DefMI->getOpcode() == TargetOpcode::G_TRUNC) {
+ if (MachineInstr *DefMI =
+ getOpcodeDef(TargetOpcode::G_TRUNC, MI.getOperand(1).getReg())) {
unsigned DstReg = MI.getOperand(0).getReg();
LLT DstTy = MRI.getType(DstReg);
if (isInstUnsupported(TargetOpcode::G_SHL, DstTy) ||
@@ -106,6 +106,29 @@ public:
markInstAndDefDead(MI, *DefMI, DeadInsts);
return true;
}
+ return tryFoldImplicitDef(MI, DeadInsts);
+ }
+
+ /// Try to fold sb = EXTEND (G_IMPLICIT_DEF sa) -> sb = G_IMPLICIT_DEF
+ bool tryFoldImplicitDef(MachineInstr &MI,
+ SmallVectorImpl<MachineInstr *> &DeadInsts) {
+ unsigned Opcode = MI.getOpcode();
+ if (Opcode != TargetOpcode::G_ANYEXT && Opcode != TargetOpcode::G_ZEXT &&
+ Opcode != TargetOpcode::G_SEXT)
+ return false;
+
+ if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF,
+ MI.getOperand(1).getReg())) {
+ unsigned DstReg = MI.getOperand(0).getReg();
+ LLT DstTy = MRI.getType(DstReg);
+ if (isInstUnsupported(TargetOpcode::G_IMPLICIT_DEF, DstTy))
+ return false;
+ DEBUG(dbgs() << ".. Combine EXT(IMPLICIT_DEF) " << MI;);
+ Builder.setInstr(MI);
+ Builder.buildInstr(TargetOpcode::G_IMPLICIT_DEF, DstReg);
+ markInstAndDefDead(MI, *DefMI, DeadInsts);
+ return true;
+ }
return false;
}
@@ -200,6 +223,12 @@ public:
return tryCombineSExt(MI, DeadInsts);
case TargetOpcode::G_UNMERGE_VALUES:
return tryCombineMerges(MI, DeadInsts);
+ case TargetOpcode::G_TRUNC: {
+ bool Changed = false;
+ for (auto &Use : MRI.use_instructions(MI.getOperand(0).getReg()))
+ Changed |= tryCombineInstruction(Use, DeadInsts);
+ return Changed;
+ }
}
}
@@ -219,6 +248,23 @@ private:
return Action.first == LegalizerInfo::LegalizeAction::Unsupported ||
Action.first == LegalizerInfo::LegalizeAction::NotFound;
}
+ /// See if Reg is defined by an single def instruction that is
+ /// Opcode. Also try to do trivial folding if it's a COPY with
+ /// same types. Returns null otherwise.
+ MachineInstr *getOpcodeDef(unsigned Opcode, unsigned Reg) {
+ auto *DefMI = MRI.getVRegDef(Reg);
+ auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
+ if (!DstTy.isValid())
+ return nullptr;
+ while (DefMI->getOpcode() == TargetOpcode::COPY) {
+ unsigned SrcReg = DefMI->getOperand(1).getReg();
+ auto SrcTy = MRI.getType(SrcReg);
+ if (!SrcTy.isValid() || SrcTy != DstTy)
+ break;
+ DefMI = MRI.getVRegDef(SrcReg);
+ }
+ return DefMI->getOpcode() == Opcode ? DefMI : nullptr;
+ }
};
} // namespace llvm
Removed: llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerCombiner.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerCombiner.h?rev=318209&view=auto
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerCombiner.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/LegalizerCombiner.h (removed)
@@ -1,224 +0,0 @@
-//===-- llvm/CodeGen/GlobalISel/LegalizerCombiner.h --===========//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-// This file contains some helper functions which try to cleanup artifacts
-// such as G_TRUNCs/G_[ZSA]EXTENDS that were created during legalization to make
-// the types match. This file also contains some combines of merges that happens
-// at the end of the legalization.
-//===----------------------------------------------------------------------===//
-
-#include "llvm/CodeGen/GlobalISel/Legalizer.h"
-#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
-#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
-#include "llvm/CodeGen/GlobalISel/Utils.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Support/Debug.h"
-
-#define DEBUG_TYPE "legalizer"
-
-namespace llvm {
-class LegalizerCombiner {
- MachineIRBuilder &Builder;
- MachineRegisterInfo &MRI;
- const LegalizerInfo &LI;
-
-public:
- LegalizerCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI,
- const LegalizerInfo &LI)
- : Builder(B), MRI(MRI), LI(LI) {}
-
- bool tryCombineAnyExt(MachineInstr &MI,
- SmallVectorImpl<MachineInstr *> &DeadInsts) {
- if (MI.getOpcode() != TargetOpcode::G_ANYEXT)
- return false;
- MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(1).getReg());
- if (DefMI->getOpcode() == TargetOpcode::G_TRUNC) {
- DEBUG(dbgs() << ".. Combine MI: " << MI;);
- unsigned DstReg = MI.getOperand(0).getReg();
- unsigned SrcReg = DefMI->getOperand(1).getReg();
- Builder.setInstr(MI);
- // We get a copy/trunc/extend depending on the sizes
- Builder.buildAnyExtOrTrunc(DstReg, SrcReg);
- markInstAndDefDead(MI, *DefMI, DeadInsts);
- return true;
- }
- return false;
- }
-
- bool tryCombineZExt(MachineInstr &MI,
- SmallVectorImpl<MachineInstr *> &DeadInsts) {
-
- if (MI.getOpcode() != TargetOpcode::G_ZEXT)
- return false;
- MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(1).getReg());
- if (DefMI->getOpcode() == TargetOpcode::G_TRUNC) {
- unsigned DstReg = MI.getOperand(0).getReg();
- LLT DstTy = MRI.getType(DstReg);
- if (isInstUnsupported(TargetOpcode::G_AND, DstTy) ||
- isInstUnsupported(TargetOpcode::G_CONSTANT, DstTy))
- return false;
- DEBUG(dbgs() << ".. Combine MI: " << MI;);
- Builder.setInstr(MI);
- unsigned ZExtSrc = MI.getOperand(1).getReg();
- LLT ZExtSrcTy = MRI.getType(ZExtSrc);
- APInt Mask = APInt::getAllOnesValue(ZExtSrcTy.getSizeInBits());
- auto MaskCstMIB = Builder.buildConstant(DstTy, Mask.getZExtValue());
- unsigned TruncSrc = DefMI->getOperand(1).getReg();
- // We get a copy/trunc/extend depending on the sizes
- auto SrcCopyOrTrunc = Builder.buildAnyExtOrTrunc(DstTy, TruncSrc);
- Builder.buildAnd(DstReg, SrcCopyOrTrunc, MaskCstMIB);
- markInstAndDefDead(MI, *DefMI, DeadInsts);
- return true;
- }
- return false;
- }
-
- bool tryCombineSExt(MachineInstr &MI,
- SmallVectorImpl<MachineInstr *> &DeadInsts) {
-
- if (MI.getOpcode() != TargetOpcode::G_SEXT)
- return false;
- MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(1).getReg());
- if (DefMI->getOpcode() == TargetOpcode::G_TRUNC) {
- unsigned DstReg = MI.getOperand(0).getReg();
- LLT DstTy = MRI.getType(DstReg);
- if (isInstUnsupported(TargetOpcode::G_SHL, DstTy) ||
- isInstUnsupported(TargetOpcode::G_ASHR, DstTy) ||
- isInstUnsupported(TargetOpcode::G_CONSTANT, DstTy))
- return false;
- DEBUG(dbgs() << ".. Combine MI: " << MI;);
- Builder.setInstr(MI);
- unsigned SExtSrc = MI.getOperand(1).getReg();
- LLT SExtSrcTy = MRI.getType(SExtSrc);
- unsigned SizeDiff = DstTy.getSizeInBits() - SExtSrcTy.getSizeInBits();
- auto SizeDiffMIB = Builder.buildConstant(DstTy, SizeDiff);
- unsigned TruncSrcReg = DefMI->getOperand(1).getReg();
- // We get a copy/trunc/extend depending on the sizes
- auto SrcCopyExtOrTrunc = Builder.buildAnyExtOrTrunc(DstTy, TruncSrcReg);
- auto ShlMIB = Builder.buildInstr(TargetOpcode::G_SHL, DstTy,
- SrcCopyExtOrTrunc, SizeDiffMIB);
- Builder.buildInstr(TargetOpcode::G_ASHR, DstReg, ShlMIB, SizeDiffMIB);
- markInstAndDefDead(MI, *DefMI, DeadInsts);
- return true;
- }
- return false;
- }
-
- bool tryCombineMerges(MachineInstr &MI,
- SmallVectorImpl<MachineInstr *> &DeadInsts) {
-
- if (MI.getOpcode() != TargetOpcode::G_UNMERGE_VALUES)
- return false;
-
- unsigned NumDefs = MI.getNumOperands() - 1;
- unsigned SrcReg = MI.getOperand(NumDefs).getReg();
- MachineInstr *MergeI = MRI.getVRegDef(SrcReg);
- if (!MergeI || (MergeI->getOpcode() != TargetOpcode::G_MERGE_VALUES))
- return false;
-
- const unsigned NumMergeRegs = MergeI->getNumOperands() - 1;
-
- if (NumMergeRegs < NumDefs) {
- if (NumDefs % NumMergeRegs != 0)
- return false;
-
- Builder.setInstr(MI);
- // Transform to UNMERGEs, for example
- // %1 = G_MERGE_VALUES %4, %5
- // %9, %10, %11, %12 = G_UNMERGE_VALUES %1
- // to
- // %9, %10 = G_UNMERGE_VALUES %4
- // %11, %12 = G_UNMERGE_VALUES %5
-
- const unsigned NewNumDefs = NumDefs / NumMergeRegs;
- for (unsigned Idx = 0; Idx < NumMergeRegs; ++Idx) {
- SmallVector<unsigned, 2> DstRegs;
- for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs;
- ++j, ++DefIdx)
- DstRegs.push_back(MI.getOperand(DefIdx).getReg());
-
- Builder.buildUnmerge(DstRegs, MergeI->getOperand(Idx + 1).getReg());
- }
-
- } else if (NumMergeRegs > NumDefs) {
- if (NumMergeRegs % NumDefs != 0)
- return false;
-
- Builder.setInstr(MI);
- // Transform to MERGEs
- // %6 = G_MERGE_VALUES %17, %18, %19, %20
- // %7, %8 = G_UNMERGE_VALUES %6
- // to
- // %7 = G_MERGE_VALUES %17, %18
- // %8 = G_MERGE_VALUES %19, %20
-
- const unsigned NumRegs = NumMergeRegs / NumDefs;
- for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) {
- SmallVector<unsigned, 2> Regs;
- for (unsigned j = 0, Idx = NumRegs * DefIdx + 1; j < NumRegs;
- ++j, ++Idx)
- Regs.push_back(MergeI->getOperand(Idx).getReg());
-
- Builder.buildMerge(MI.getOperand(DefIdx).getReg(), Regs);
- }
-
- } else {
- // FIXME: is a COPY appropriate if the types mismatch? We know both
- // registers are allocatable by now.
- if (MRI.getType(MI.getOperand(0).getReg()) !=
- MRI.getType(MergeI->getOperand(1).getReg()))
- return false;
-
- for (unsigned Idx = 0; Idx < NumDefs; ++Idx)
- MRI.replaceRegWith(MI.getOperand(Idx).getReg(),
- MergeI->getOperand(Idx + 1).getReg());
- }
-
- markInstAndDefDead(MI, *MergeI, DeadInsts);
- return true;
- }
-
- /// Try to combine away MI.
- /// Returns true if it combined away the MI.
- /// Adds instructions that are dead as a result of the combine
- /// into DeadInsts, which can include MI.
- bool tryCombineInstruction(MachineInstr &MI,
- SmallVectorImpl<MachineInstr *> &DeadInsts) {
- switch (MI.getOpcode()) {
- default:
- return false;
- case TargetOpcode::G_ANYEXT:
- return tryCombineAnyExt(MI, DeadInsts);
- case TargetOpcode::G_ZEXT:
- return tryCombineZExt(MI, DeadInsts);
- case TargetOpcode::G_SEXT:
- return tryCombineSExt(MI, DeadInsts);
- case TargetOpcode::G_UNMERGE_VALUES:
- return tryCombineMerges(MI, DeadInsts);
- }
- }
-
-private:
- /// Mark MI as dead. If a def of one of MI's operands, DefMI, would also be
- /// dead due to MI being killed, then mark DefMI as dead too.
- void markInstAndDefDead(MachineInstr &MI, MachineInstr &DefMI,
- SmallVectorImpl<MachineInstr *> &DeadInsts) {
- DeadInsts.push_back(&MI);
- if (MRI.hasOneUse(DefMI.getOperand(0).getReg()))
- DeadInsts.push_back(&DefMI);
- }
- /// Checks if the target legalizer info has specified anything about the
- /// instruction, or if unsupported.
- bool isInstUnsupported(unsigned Opcode, const LLT &DstTy) const {
- auto Action = LI.getAction({Opcode, 0, DstTy});
- return Action.first == LegalizerInfo::LegalizeAction::Unsupported ||
- Action.first == LegalizerInfo::LegalizeAction::NotFound;
- }
-};
-
-} // namespace llvm
Modified: llvm/trunk/lib/CodeGen/GlobalISel/Legalizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/Legalizer.cpp?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/Legalizer.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/Legalizer.cpp Tue Nov 14 14:42:19 2017
@@ -14,10 +14,12 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/GlobalISel/Legalizer.h"
+#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/ADT/SetVector.h"
-#include "llvm/CodeGen/GlobalISel/LegalizerCombiner.h"
+#include "llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h"
#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
+#include "llvm/CodeGen/GlobalISel/GISelWorkList.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
@@ -52,6 +54,20 @@ void Legalizer::getAnalysisUsage(Analysi
void Legalizer::init(MachineFunction &MF) {
}
+static bool isArtifact(const MachineInstr &MI) {
+ switch (MI.getOpcode()) {
+ default:
+ return false;
+ case TargetOpcode::G_TRUNC:
+ case TargetOpcode::G_ZEXT:
+ case TargetOpcode::G_ANYEXT:
+ case TargetOpcode::G_SEXT:
+ case TargetOpcode::G_MERGE_VALUES:
+ case TargetOpcode::G_UNMERGE_VALUES:
+ return true;
+ }
+}
+
bool Legalizer::runOnMachineFunction(MachineFunction &MF) {
// If the ISel pipeline failed, do not bother running that pass.
if (MF.getProperties().hasProperty(
@@ -63,114 +79,108 @@ bool Legalizer::runOnMachineFunction(Mac
MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
LegalizerHelper Helper(MF);
- // FIXME: an instruction may need more than one pass before it is legal. For
- // example on most architectures <3 x i3> is doubly-illegal. It would
- // typically proceed along a path like: <3 x i3> -> <3 x i8> -> <8 x i8>. We
- // probably want a worklist of instructions rather than naive iterate until
- // convergence for performance reasons.
- bool Changed = false;
- MachineBasicBlock::iterator NextMI;
- using VecType = SmallSetVector<MachineInstr *, 8>;
- VecType WorkList;
- VecType CombineList;
- for (auto &MBB : MF) {
- for (auto MI = MBB.begin(); MI != MBB.end(); MI = NextMI) {
- // Get the next Instruction before we try to legalize, because there's a
- // good chance MI will be deleted.
- NextMI = std::next(MI);
+ const size_t NumBlocks = MF.size();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
+ // Populate Insts
+ GISelWorkList<256> InstList;
+ GISelWorkList<128> ArtifactList;
+ ReversePostOrderTraversal<MachineFunction *> RPOT(&MF);
+ // Perform legalization bottom up so we can DCE as we legalize.
+ // Traverse BB in RPOT and within each basic block, add insts top down,
+ // so when we pop_back_val in the legalization process, we traverse bottom-up.
+ for (auto *MBB : RPOT) {
+ if (MBB->empty())
+ continue;
+ for (MachineInstr &MI : *MBB) {
// Only legalize pre-isel generic instructions: others don't have types
// and are assumed to be legal.
- if (!isPreISelGenericOpcode(MI->getOpcode()))
+ if (!isPreISelGenericOpcode(MI.getOpcode()))
continue;
- unsigned NumNewInsns = 0;
- WorkList.clear();
- CombineList.clear();
- Helper.MIRBuilder.recordInsertions([&](MachineInstr *MI) {
- // Only legalize pre-isel generic instructions.
- // Legalization process could generate Target specific pseudo
- // instructions with generic types. Don't record them
- if (isPreISelGenericOpcode(MI->getOpcode())) {
- ++NumNewInsns;
- WorkList.insert(MI);
- CombineList.insert(MI);
- }
- });
- WorkList.insert(&*MI);
- LegalizerCombiner C(Helper.MIRBuilder, MF.getRegInfo(),
- Helper.getLegalizerInfo());
- bool Changed = false;
- LegalizerHelper::LegalizeResult Res;
- do {
- assert(!WorkList.empty() && "Expecting illegal ops");
- while (!WorkList.empty()) {
- NumNewInsns = 0;
- MachineInstr *CurrInst = WorkList.pop_back_val();
- Res = Helper.legalizeInstrStep(*CurrInst);
- // Error out if we couldn't legalize this instruction. We may want to
- // fall back to DAG ISel instead in the future.
- if (Res == LegalizerHelper::UnableToLegalize) {
- Helper.MIRBuilder.stopRecordingInsertions();
- if (Res == LegalizerHelper::UnableToLegalize) {
- reportGISelFailure(MF, TPC, MORE, "gisel-legalize",
- "unable to legalize instruction", *CurrInst);
- return false;
- }
- }
- Changed |= Res == LegalizerHelper::Legalized;
- // If CurrInst was legalized, there's a good chance that it might have
- // been erased. So remove it from the Combine List.
- if (Res == LegalizerHelper::Legalized)
- CombineList.remove(CurrInst);
-
-#ifndef NDEBUG
- if (NumNewInsns)
- for (unsigned I = WorkList.size() - NumNewInsns,
- E = WorkList.size();
- I != E; ++I)
- DEBUG(dbgs() << ".. .. New MI: " << *WorkList[I];);
-#endif
- }
- // Do the combines.
- while (!CombineList.empty()) {
- NumNewInsns = 0;
- MachineInstr *CurrInst = CombineList.pop_back_val();
- SmallVector<MachineInstr *, 4> DeadInstructions;
- Changed |= C.tryCombineInstruction(*CurrInst, DeadInstructions);
- for (auto *DeadMI : DeadInstructions) {
- DEBUG(dbgs() << ".. Erasing Dead Instruction " << *DeadMI);
- CombineList.remove(DeadMI);
- WorkList.remove(DeadMI);
- DeadMI->eraseFromParent();
- }
-#ifndef NDEBUG
- if (NumNewInsns)
- for (unsigned I = CombineList.size() - NumNewInsns,
- E = CombineList.size();
- I != E; ++I)
- DEBUG(dbgs() << ".. .. Combine New MI: " << *CombineList[I];);
-#endif
- }
- } while (!WorkList.empty());
-
- Helper.MIRBuilder.stopRecordingInsertions();
+ if (isArtifact(MI))
+ ArtifactList.insert(&MI);
+ else
+ InstList.insert(&MI);
}
}
+ Helper.MIRBuilder.recordInsertions([&](MachineInstr *MI) {
+ // Only legalize pre-isel generic instructions.
+ // Legalization process could generate Target specific pseudo
+ // instructions with generic types. Don't record them
+ if (isPreISelGenericOpcode(MI->getOpcode())) {
+ if (isArtifact(*MI))
+ ArtifactList.insert(MI);
+ else
+ InstList.insert(MI);
+ }
+ DEBUG(dbgs() << ".. .. New MI: " << *MI;);
+ });
+ const LegalizerInfo &LInfo(Helper.getLegalizerInfo());
+ LegalizationArtifactCombiner ArtCombiner(Helper.MIRBuilder, MF.getRegInfo(), LInfo);
+ auto RemoveDeadInstFromLists = [&InstList,
+ &ArtifactList](MachineInstr *DeadMI) {
+ InstList.remove(DeadMI);
+ ArtifactList.remove(DeadMI);
+ };
+ bool Changed = false;
+ do {
+ while (!InstList.empty()) {
+ MachineInstr &MI = *InstList.pop_back_val();
+ assert(isPreISelGenericOpcode(MI.getOpcode()) && "Expecting generic opcode");
+ if (isTriviallyDead(MI, MRI)) {
+ DEBUG(dbgs() << MI << "Is dead; erasing.\n");
+ MI.eraseFromParentAndMarkDBGValuesForRemoval();
+ continue;
+ }
- MachineRegisterInfo &MRI = MF.getRegInfo();
- MachineIRBuilder MIRBuilder(MF);
- LegalizerCombiner C(MIRBuilder, MRI, Helper.getLegalizerInfo());
- for (auto &MBB : MF) {
- for (auto MI = MBB.begin(); MI != MBB.end(); MI = NextMI) {
- // Get the next Instruction before we try to legalize, because there's a
- // good chance MI will be deleted.
- // TOOD: Perhaps move this to a combiner pass later?.
- NextMI = std::next(MI);
- SmallVector<MachineInstr *, 4> DeadInsts;
- Changed |= C.tryCombineMerges(*MI, DeadInsts);
- for (auto *DeadMI : DeadInsts)
- DeadMI->eraseFromParent();
+ // Do the legalization for this instruction.
+ auto Res = Helper.legalizeInstrStep(MI);
+ // Error out if we couldn't legalize this instruction. We may want to
+ // fall back to DAG ISel instead in the future.
+ if (Res == LegalizerHelper::UnableToLegalize) {
+ Helper.MIRBuilder.stopRecordingInsertions();
+ reportGISelFailure(MF, TPC, MORE, "gisel-legalize",
+ "unable to legalize instruction", MI);
+ return false;
+ }
+ Changed |= Res == LegalizerHelper::Legalized;
+ }
+ while (!ArtifactList.empty()) {
+ MachineInstr &MI = *ArtifactList.pop_back_val();
+ assert(isPreISelGenericOpcode(MI.getOpcode()) && "Expecting generic opcode");
+ if (isTriviallyDead(MI, MRI)) {
+ DEBUG(dbgs() << MI << "Is dead; erasing.\n");
+ RemoveDeadInstFromLists(&MI);
+ MI.eraseFromParentAndMarkDBGValuesForRemoval();
+ continue;
+ }
+ SmallVector<MachineInstr *, 4> DeadInstructions;
+ if (ArtCombiner.tryCombineInstruction(MI, DeadInstructions)) {
+ for (auto *DeadMI : DeadInstructions) {
+ DEBUG(dbgs() << ".. Erasing Dead Instruction " << *DeadMI);
+ RemoveDeadInstFromLists(DeadMI);
+ DeadMI->eraseFromParentAndMarkDBGValuesForRemoval();
+ }
+ Changed = true;
+ continue;
+ }
+ // If this was not an artifact (that could be combined away), this might
+ // need special handling. Add it to InstList, so when it's processed
+ // there, it has to be legal or specially handled.
+ else
+ InstList.insert(&MI);
}
+ } while (!InstList.empty());
+
+ // For now don't support if new blocks are inserted - we would need to fix the
+ // outerloop for that.
+ if (MF.size() != NumBlocks) {
+ MachineOptimizationRemarkMissed R("gisel-legalize", "GISelFailure",
+ MF.getFunction()->getSubprogram(),
+ /*MBB=*/nullptr);
+ R << "inserting blocks is not supported yet";
+ reportGISelFailure(MF, TPC, MORE, R);
+ return false;
}
return Changed;
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll Tue Nov 14 14:42:19 2017
@@ -63,19 +63,21 @@ false:
}
; General legalizer inability to handle types whose size wasn't a power of 2.
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg1<def>(s42) = G_LOAD %vreg0; mem:LD6[%addr](align=8) (in function: odd_type)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg1, %vreg0; mem:ST6[%addr](align=8) (in function: odd_type)
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_type
; FALLBACK-WITH-REPORT-OUT-LABEL: odd_type:
define void @odd_type(i42* %addr) {
%val42 = load i42, i42* %addr
+ store i42 %val42, i42* %addr
ret void
}
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg1<def>(<7 x s32>) = G_LOAD %vreg0; mem:LD28[%addr](align=32) (in function: odd_vector)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg1, %vreg0; mem:ST28[%addr](align=32) (in function: odd_vector)
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_vector
; FALLBACK-WITH-REPORT-OUT-LABEL: odd_vector:
define void @odd_vector(<7 x i32>* %addr) {
%vec = load <7 x i32>, <7 x i32>* %addr
+ store <7 x i32> %vec, <7 x i32>* %addr
ret void
}
@@ -146,6 +148,7 @@ define void @vector_of_pointers_extracte
block:
%dummy = extractelement <2 x i16*> %vec, i32 0
+ store i16* %dummy, i16** undef
ret void
end:
@@ -153,7 +156,7 @@ end:
br label %block
}
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg0<def>(<2 x p0>) = G_INSERT_VECTOR_ELT %vreg1, %vreg2, %vreg3; (in function: vector_of_pointers_insertelement
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg0, %vreg4; mem:ST16[undef] (in function: vector_of_pointers_insertelement)
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for vector_of_pointers_insertelement
; FALLBACK-WITH-REPORT-OUT-LABEL: vector_of_pointers_insertelement:
define void @vector_of_pointers_insertelement() {
@@ -161,6 +164,7 @@ define void @vector_of_pointers_insertel
block:
%dummy = insertelement <2 x i16*> %vec, i16* null, i32 0
+ store <2 x i16*> %dummy, <2 x i16*>* undef
ret void
end:
@@ -168,41 +172,44 @@ end:
br label %block
}
-; FALLBACK-WITH-REPORT-ERR-G_IMPLICIT_DEF-LEGALIZABLE: (FIXME: this is what is expected once we can legalize non-pow-of-2 G_IMPLICIT_DEF) remark: <unknown>:0:0: unable to legalize instruction: %vreg1<def>(s96) = G_INSERT %vreg2, %vreg0, 0; (in function: nonpow2_insertvalue_narrowing
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg2<def>(s96) = G_IMPLICIT_DEF; (in function: nonpow2_insertvalue_narrowing
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg1, %vreg3; mem:ST12[undef](align=4) (in function: nonpow2_insertvalue_narrowing)
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_insertvalue_narrowing
; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_insertvalue_narrowing:
%struct96 = type { float, float, float }
define void @nonpow2_insertvalue_narrowing(float %a) {
%dummy = insertvalue %struct96 undef, float %a, 0
+ store %struct96 %dummy, %struct96* undef
ret void
}
-; FALLBACK-WITH-REPORT-ERR remark: <unknown>:0:0: unable to legalize instruction: %vreg3<def>(s96) = G_ADD %vreg2, %vreg2; (in function: nonpow2_add_narrowing
+; FALLBACK-WITH-REPORT-ERR remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg3, %vreg4; mem:ST12[undef](align=16) (in function: nonpow2_add_narrowing)
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_add_narrowing
; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_add_narrowing:
define void @nonpow2_add_narrowing() {
%a = add i128 undef, undef
%b = trunc i128 %a to i96
%dummy = add i96 %b, %b
+ store i96 %dummy, i96* undef
ret void
}
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg3<def>(s96) = G_OR %vreg2, %vreg2; (in function: nonpow2_or_narrowing
+; FALLBACK-WITH-REPORT-ERR remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg3, %vreg4; mem:ST12[undef](align=16) (in function: nonpow2_add_narrowing)
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_or_narrowing
; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_or_narrowing:
define void @nonpow2_or_narrowing() {
%a = add i128 undef, undef
%b = trunc i128 %a to i96
%dummy = or i96 %b, %b
+ store i96 %dummy, i96* undef
ret void
}
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg0<def>(s96) = G_LOAD %vreg1; mem:LD12[undef](align=16) (in function: nonpow2_load_narrowing
+; FALLBACK-WITH-REPORT-ERR remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg0, %vreg1; mem:ST12[undef](align=16) (in function: nonpow2_load_narrowing)
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_load_narrowing
; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_load_narrowing:
define void @nonpow2_load_narrowing() {
%dummy = load i96, i96* undef
+ store i96 %dummy, i96* undef
ret void
}
@@ -216,7 +223,7 @@ define void @nonpow2_store_narrowing(i96
ret void
}
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg0<def>(s96) = G_CONSTANT 0; (in function: nonpow2_constant_narrowing
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg0, %vreg1; mem:ST12[undef](align=16) (in function: nonpow2_constant_narrowing)
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_constant_narrowing
; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_constant_narrowing:
define void @nonpow2_constant_narrowing() {
@@ -227,10 +234,12 @@ define void @nonpow2_constant_narrowing(
; Currently can't handle vector lengths that aren't an exact multiple of
; natively supported vector lengths. Test that the fall-back works for those.
; FALLBACK-WITH-REPORT-ERR-G_IMPLICIT_DEF-LEGALIZABLE: (FIXME: this is what is expected once we can legalize non-pow-of-2 G_IMPLICIT_DEF) remark: <unknown>:0:0: unable to legalize instruction: %vreg1<def>(<7 x s64>) = G_ADD %vreg0, %vreg0; (in function: nonpow2_vector_add_fewerelements
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg0<def>(<7 x s64>) = G_IMPLICIT_DEF; (in function: nonpow2_vector_add_fewerelements
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg2<def>(s64) = G_EXTRACT_VECTOR_ELT %vreg1, %vreg3; (in function: nonpow2_vector_add_fewerelements)
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for nonpow2_vector_add_fewerelements
; FALLBACK-WITH-REPORT-OUT-LABEL: nonpow2_vector_add_fewerelements:
define void @nonpow2_vector_add_fewerelements() {
%dummy = add <7 x i64> undef, undef
+ %ex = extractelement <7 x i64> %dummy, i64 0
+ store i64 %ex, i64* undef
ret void
}
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir Tue Nov 14 14:42:19 2017
@@ -1,4 +1,4 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
@@ -28,16 +28,6 @@
---
name: test_scalar_add_big
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
- - { id: 6, class: _ }
- - { id: 7, class: _ }
- - { id: 8, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
@@ -53,14 +43,14 @@ body: |
; CHECK: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY3]], [[UADDE1]]
; CHECK: %x0 = COPY [[UADDE]](s64)
; CHECK: %x1 = COPY [[UADDE2]](s64)
- %0(s64) = COPY %x0
- %1(s64) = COPY %x1
- %2(s64) = COPY %x2
- %3(s64) = COPY %x3
- %4(s128) = G_MERGE_VALUES %0, %1
- %5(s128) = G_MERGE_VALUES %2, %3
- %6(s128) = G_ADD %4, %5
- %7(s64), %8(s64) = G_UNMERGE_VALUES %6
+ %0:_(s64) = COPY %x0
+ %1:_(s64) = COPY %x1
+ %2:_(s64) = COPY %x2
+ %3:_(s64) = COPY %x3
+ %4:_(s128) = G_MERGE_VALUES %0, %1
+ %5:_(s128) = G_MERGE_VALUES %2, %3
+ %6:_(s128) = G_ADD %4, %5
+ %7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %6
%x0 = COPY %7
%x1 = COPY %8
...
@@ -110,13 +100,6 @@ body: |
---
name: test_scalar_add_small
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
@@ -127,30 +110,19 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[ADD]](s32)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC2]](s8)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
; CHECK: %x0 = COPY [[ANYEXT]](s64)
- %0(s64) = COPY %x0
- %1(s64) = COPY %x1
- %2(s8) = G_TRUNC %0
- %3(s8) = G_TRUNC %1
- %4(s8) = G_ADD %2, %3
- %5(s64) = G_ANYEXT %4
+ %0:_(s64) = COPY %x0
+ %1:_(s64) = COPY %x1
+ %2:_(s8) = G_TRUNC %0
+ %3:_(s8) = G_TRUNC %1
+ %4:_(s8) = G_ADD %2, %3
+ %5:_(s64) = G_ANYEXT %4
%x0 = COPY %5
...
---
name: test_vector_add
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
- - { id: 6, class: _ }
- - { id: 7, class: _ }
- - { id: 8, class: _ }
body: |
bb.0.entry:
liveins: %q0, %q1, %q2, %q3
@@ -164,14 +136,14 @@ body: |
; CHECK: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY1]], [[COPY3]]
; CHECK: %q0 = COPY [[ADD]](<2 x s64>)
; CHECK: %q1 = COPY [[ADD1]](<2 x s64>)
- %0(<2 x s64>) = COPY %q0
- %1(<2 x s64>) = COPY %q1
- %2(<2 x s64>) = COPY %q2
- %3(<2 x s64>) = COPY %q3
- %4(<4 x s64>) = G_MERGE_VALUES %0, %1
- %5(<4 x s64>) = G_MERGE_VALUES %2, %3
- %6(<4 x s64>) = G_ADD %4, %5
- %7(<2 x s64>), %8(<2 x s64>) = G_UNMERGE_VALUES %6
+ %0:_(<2 x s64>) = COPY %q0
+ %1:_(<2 x s64>) = COPY %q1
+ %2:_(<2 x s64>) = COPY %q2
+ %3:_(<2 x s64>) = COPY %q3
+ %4:_(<4 x s64>) = G_MERGE_VALUES %0, %1
+ %5:_(<4 x s64>) = G_MERGE_VALUES %2, %3
+ %6:_(<4 x s64>) = G_ADD %4, %5
+ %7:_(<2 x s64>), %8:_(<2 x s64>) = G_UNMERGE_VALUES %6
%q0 = COPY %7
%q1 = COPY %8
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir Tue Nov 14 14:42:19 2017
@@ -19,6 +19,7 @@ registers:
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
+ - { id: 6, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
@@ -26,18 +27,20 @@ body: |
; CHECK-LABEL: name: test_scalar_and_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[TRUNC2]]
- ; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[AND]](s32)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s8)
- ; CHECK: %x0 = COPY [[ANYEXT]](s64)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[TRUNC1]]
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
+ ; CHECK: %w0 = COPY [[COPY2]](s32)
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
+ ; CHECK: %x0 = COPY [[COPY3]](s64)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
%4(s8) = G_AND %2, %3
+ %6(s32) = G_ANYEXT %4
+ %w0 = COPY %6
%5(s64) = G_ANYEXT %2
%x0 = COPY %5
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir Tue Nov 14 14:42:19 2017
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
@@ -23,29 +24,48 @@ registers:
- { id: 8, class: _ }
- { id: 9, class: _ }
- { id: 10, class: _ }
+ - { id: 11, class: _ }
+ - { id: 12, class: _ }
+ - { id: 13, class: _ }
+ - { id: 14, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
+ ; CHECK-LABEL: name: test_icmp
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x0
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[COPY]](s64), [[COPY1]]
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+ ; CHECK: %w0 = COPY [[COPY2]](s32)
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
+ ; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[AND1]]
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+ ; CHECK: %w0 = COPY [[COPY3]](s32)
+ ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
+ ; CHECK: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[INTTOPTR]](p0), [[INTTOPTR]]
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
+ ; CHECK: %w0 = COPY [[COPY4]](s32)
%0(s64) = COPY %x0
%1(s64) = COPY %x0
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
- ; CHECK: [[CMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), %0(s64), %1
- ; CHECK: [[CMP_T1:%[0-9]+]]:_(s1) = G_TRUNC [[CMP1]]
%4(s1) = G_ICMP intpred(sge), %0, %1
+ %11(s32) = G_ANYEXT %4
+ %w0 = COPY %11
- ; CHECK: [[CSTMASK1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_TRUNC %0(s64)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[T1]], [[CSTMASK1]]
- ; CHECK: [[CSTMASK2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[T2:%[0-9]+]]:_(s32) = G_TRUNC %1(s64)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[T2]], [[CSTMASK2]]
- ; CHECK: [[CMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND1]](s32), [[AND2]]
- ; CHECK: [[CMP_T2:%[0-9]+]]:_(s1) = G_TRUNC [[CMP2]]
%8(s1) = G_ICMP intpred(ult), %2, %3
+ %12(s32) = G_ANYEXT %8
+ %w0 = COPY %12
%9(p0) = G_INTTOPTR %0(s64)
%10(s1) = G_ICMP intpred(eq), %9(p0), %9(p0)
+ %14(s32) = G_ANYEXT %10
+ %w0 = COPY %14
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir Tue Nov 14 14:42:19 2017
@@ -29,7 +29,10 @@ body: |
%1:_(s32) = G_ADD %0, %0
%2:_(s64) = G_MERGE_VALUES %0, %1
%3:_(s1) = G_EXTRACT %2, 0
+ %5:_(s32) = G_ANYEXT %3
+ %w0 = COPY %5
%4:_(s64) = G_EXTRACT %2, 0
+ %x0 = COPY %4
...
---
@@ -48,6 +51,7 @@ body: |
%2:_(s64) = G_MERGE_VALUES %0, %1
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2
%5:_(s32) = G_ADD %3, %4
+ %w0 = COPY %5
...
---
@@ -65,6 +69,7 @@ body: |
%1:_(s128) = G_MERGE_VALUES %0, %0
%2:_(s64) = G_EXTRACT %1, 0
%3:_(s64) = G_ADD %2, %2
+ %w0 = COPY %3
...
---
@@ -83,6 +88,7 @@ body: |
%2:_(s64) = G_MERGE_VALUES %0, %1
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2
%5:_(s32) = G_ADD %3, %4
+ %w0 = COPY %5
...
---
@@ -102,4 +108,5 @@ body: |
%2:_(s32) = G_UNMERGE_VALUES %1
%3:_(s32) = G_MUL %2, %2
%4:_(s32) = G_ADD %2, %3
+ %w0 = COPY %4
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir Tue Nov 14 14:42:19 2017
@@ -30,20 +30,35 @@ body: |
; CHECK-LABEL: name: test_constant
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK: %w0 = COPY [[COPY]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[C1]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK: %w0 = COPY [[COPY1]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
+ ; CHECK: %w0 = COPY [[COPY2]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK: %w0 = COPY [[C3]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK: %x0 = COPY [[C4]](s64)
; CHECK: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
+ ; CHECK: %x0 = COPY [[C5]](s64)
%0(s1) = G_CONSTANT i1 0
+ %6:_(s32) = G_ANYEXT %0
+ %w0 = COPY %6
%1(s8) = G_CONSTANT i8 42
+ %7:_(s32) = G_ANYEXT %1
+ %w0 = COPY %7
%2(s16) = G_CONSTANT i16 65535
+ %8:_(s32) = G_ANYEXT %2
+ %w0 = COPY %8
%3(s32) = G_CONSTANT i32 -1
+ %w0 = COPY %3
%4(s64) = G_CONSTANT i64 1
+ %x0 = COPY %4
%5(s64) = G_CONSTANT i64 0
+ %x0 = COPY %5
...
---
@@ -57,12 +72,20 @@ body: |
; CHECK-LABEL: name: test_fconstant
; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+ ; CHECK: %w0 = COPY [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
+ ; CHECK: %x0 = COPY [[C1]](s64)
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT half 0xH0000
; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[C2]](s32)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
+ ; CHECK: %w0 = COPY [[ANYEXT]](s32)
%0(s32) = G_FCONSTANT float 1.0
+ %w0 = COPY %0
%1(s64) = G_FCONSTANT double 2.0
+ %x0 = COPY %1
%2(s16) = G_FCONSTANT half 0.0
+ %3:_(s32) = G_ANYEXT %2
+ %w0 = COPY %3
...
---
@@ -74,5 +97,9 @@ body: |
; CHECK-LABEL: name: test_global
; CHECK: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @var
+ ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[GV]](p0)
+ ; CHECK: %x0 = COPY [[PTRTOINT]](s64)
%0(p0) = G_GLOBAL_VALUE @var
+ %1:_(s64) = G_PTRTOINT %0
+ %x0 = COPY %1
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mir Tue Nov 14 14:42:19 2017
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
@@ -21,35 +22,42 @@ registers:
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
+ ; CHECK-LABEL: name: test_div
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]]
+ ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]]
+ ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
+ ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
+ ; CHECK: %w0 = COPY [[COPY2]](s32)
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C2]]
+ ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C3]]
+ ; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
+ ; CHECK: %w0 = COPY [[COPY3]](s32)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
- ; CHECK: [[A:%.*]]:_(s64) = COPY %x0
- ; CHECK: [[B:%.*]]:_(s64) = COPY %x1
- ; CHECK: [[C1:%.*]]:_(s32) = G_CONSTANT i32 24
- ; CHECK: [[S1:%.*]]:_(s32) = G_TRUNC [[A]]
- ; CHECK: [[SHL1:%.*]]:_(s32) = G_SHL [[S1]], [[C1]]
- ; CHECK: [[SEXT1:%.*]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
- ; CHECK: [[C2:%.*]]:_(s32) = G_CONSTANT i32 24
- ; CHECK: [[S2:%.*]]:_(s32) = G_TRUNC [[B]]
- ; CHECK: [[SHL2:%.*]]:_(s32) = G_SHL [[S2]], [[C2]]
- ; CHECK: [[SEXT2:%.*]]:_(s32) = G_ASHR [[SHL2]], [[C2]]
- ; CHECK: [[DIV:%.*]]:_(s32) = G_SDIV [[SEXT1]], [[SEXT2]]
- ; CHECK: [[RES:%.*]]:_(s8) = G_TRUNC [[DIV]]
%4(s8) = G_SDIV %2, %3
+ %6:_(s32) = G_ANYEXT %4
+ %w0 = COPY %6
- ; CHECK: [[CMASK1:%.*]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[T1:%.*]]:_(s32) = G_TRUNC [[A]]
- ; CHECK: [[LHS32:%.*]]:_(s32) = G_AND [[T1]], [[CMASK1]]
- ; CHECK: [[CMASK2:%.*]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[T2:%.*]]:_(s32) = G_TRUNC [[B]]
- ; CHECK: [[RHS32:%.*]]:_(s32) = G_AND [[T2]], [[CMASK2]]
- ; CHECK: [[QUOT32:%[0-9]+]]:_(s32) = G_UDIV [[LHS32]], [[RHS32]]
- ; CHECK: [[RES:%[0-9]+]]:_(s8) = G_TRUNC [[QUOT32]]
%5(s8) = G_UDIV %2, %3
+ %7:_(s32) = G_ANYEXT %5
+ %w0 = COPY %7
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir Tue Nov 14 14:42:19 2017
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
@@ -34,46 +35,109 @@ registers:
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
+ ; CHECK-LABEL: name: test_ext
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: %w0 = COPY [[TRUNC]](s32)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: %w0 = COPY [[TRUNC1]](s32)
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: %w0 = COPY [[TRUNC2]](s32)
+ ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: %w0 = COPY [[TRUNC3]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
+ ; CHECK: %x0 = COPY [[COPY1]](s64)
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
+ ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C]]
+ ; CHECK: %x0 = COPY [[AND]](s64)
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
+ ; CHECK: %x0 = COPY [[COPY3]](s64)
+ ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
+ ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY4]], [[C1]]
+ ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]]
+ ; CHECK: %x0 = COPY [[ASHR]](s64)
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+ ; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC4]], [[C2]]
+ ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C2]]
+ ; CHECK: %w0 = COPY [[ASHR1]](s32)
+ ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC5]], [[C3]]
+ ; CHECK: %w0 = COPY [[AND1]](s32)
+ ; CHECK: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: %w0 = COPY [[TRUNC6]](s32)
+ ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC7]], [[C4]]
+ ; CHECK: %w0 = COPY [[AND2]](s32)
+ ; CHECK: [[TRUNC8:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: %w0 = COPY [[TRUNC8]](s32)
+ ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+ ; CHECK: [[TRUNC9:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[TRUNC9]], [[C5]]
+ ; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[SHL2]], [[C5]]
+ ; CHECK: %w0 = COPY [[ASHR2]](s32)
+ ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[TRUNC10:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[TRUNC3]]4(s32)
+ ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]]1, [[TRUNC3]]2
+ ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[TRUNC3]]3(s32)
+ ; CHECK: %w0 = COPY [[COPY6]](s32)
+ ; CHECK: [[TRUNC11:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: %w0 = COPY [[TRUNC11]](s32)
+ ; CHECK: [[TRUNC12:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: %w0 = COPY [[TRUNC12]](s32)
+ ; CHECK: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[TRUNC12]](s32)
+ ; CHECK: %x0 = COPY [[FPEXT]](s64)
%0(s64) = COPY %x0
- ; CHECK: %1:_(s1) = G_TRUNC %0
- ; CHECK: %2:_(s8) = G_TRUNC %0
- ; CHECK: %3:_(s16) = G_TRUNC %0
- ; CHECK: %4:_(s32) = G_TRUNC %0
%1(s1) = G_TRUNC %0
+ %19:_(s32) = G_ANYEXT %1
+ %w0 = COPY %19
%2(s8) = G_TRUNC %0
+ %20:_(s32) = G_ANYEXT %2
+ %w0 = COPY %20
%3(s16) = G_TRUNC %0
+ %21:_(s32) = G_ANYEXT %3
+ %w0 = COPY %21
%4(s32) = G_TRUNC %0
+ %w0 = COPY %4
- ; CHECK: %5:_(s64) = G_ANYEXT %1
- ; CHECK: %6:_(s64) = G_ZEXT %2
- ; CHECK: %7:_(s64) = G_ANYEXT %3
- ; CHECK: %8:_(s64) = G_SEXT %4
%5(s64) = G_ANYEXT %1
+ %x0 = COPY %5
%6(s64) = G_ZEXT %2
+ %x0 = COPY %6
%7(s64) = G_ANYEXT %3
+ %x0 = COPY %7
%8(s64) = G_SEXT %4
+ %x0 = COPY %8
- ; CHECK: %9:_(s32) = G_SEXT %1
- ; CHECK: %10:_(s32) = G_ZEXT %2
- ; CHECK: %11:_(s32) = G_ANYEXT %3
%9(s32) = G_SEXT %1
+ %w0 = COPY %9
%10(s32) = G_ZEXT %2
+ %w0 = COPY %10
%11(s32) = G_ANYEXT %3
+ %w0 = COPY %11
- ; CHECK: %12:_(s32) = G_ZEXT %1
- ; CHECK: %13:_(s32) = G_ANYEXT %2
- ; CHECK: %14:_(s32) = G_SEXT %3
%12(s32) = G_ZEXT %1
+ %w0 = COPY %12
%13(s32) = G_ANYEXT %2
+ %w0 = COPY %13
%14(s32) = G_SEXT %3
+ %w0 = COPY %14
- ; CHECK: %15:_(s8) = G_ZEXT %1
- ; CHECK: %16:_(s16) = G_ANYEXT %2
%15(s8) = G_ZEXT %1
+ %22:_(s32) = G_ANYEXT %15
+ %w0 = COPY %22
%16(s16) = G_ANYEXT %2
+ %23:_(s32) = G_ANYEXT %16
+ %w0 = COPY %23
- ; CHECK: %18:_(s64) = G_FPEXT %17
%17(s32) = G_TRUNC %0
+ %w0 = COPY %17
%18(s64) = G_FPEXT %17
+ %x0 = COPY %18
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir Tue Nov 14 14:42:19 2017
@@ -11,15 +11,13 @@ body: |
; value stored is forwarded directly from first load.
; CHECK-LABEL: name: test_extracts_1
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %w1
- ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY %x2
- ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY2]](p0) :: (load 16)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x2
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 16)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY2]], [[C]](s64)
+ ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64)
; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 16)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
- ; CHECK: G_STORE [[COPY3]](s64), [[COPY2]](p0) :: (store 8)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
+ ; CHECK: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store 8)
; CHECK: RET_ReallyLR
%0:_(s64) = COPY %x0
%1:_(s32) = COPY %w1
@@ -38,18 +36,16 @@ body: |
; Low extraction wipes takes whole low register. High extraction is real.
; CHECK-LABEL: name: test_extracts_2
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %w1
- ; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY %x2
- ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY2]](p0) :: (load 16)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x2
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 16)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY2]], [[C]](s64)
+ ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64)
; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 16)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[LOAD]](s64)
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[LOAD1]](s64), 0
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
- ; CHECK: G_STORE [[COPY3]](s64), [[COPY2]](p0) :: (store 8)
- ; CHECK: G_STORE [[COPY4]](s32), [[COPY2]](p0) :: (store 4)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
+ ; CHECK: G_STORE [[COPY1]](s64), [[COPY]](p0) :: (store 8)
+ ; CHECK: G_STORE [[COPY2]](s32), [[COPY]](p0) :: (store 4)
; CHECK: RET_ReallyLR
%0:_(s64) = COPY %x0
%1:_(s32) = COPY %w1
@@ -75,11 +71,13 @@ body: |
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s64), 32
; CHECK: [[EXTRACT1:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY1]](s64), 0
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[EXTRACT]](s32), [[EXTRACT1]](s32)
+ ; CHECK: %x0 = COPY [[MV]](s64)
; CHECK: RET_ReallyLR
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
%2:_(s128) = G_MERGE_VALUES %0, %1
%3:_(s64) = G_EXTRACT %2, 32
+ %x0 = COPY %3
RET_ReallyLR
...
@@ -92,13 +90,14 @@ body: |
; CHECK-LABEL: name: test_extracts_4
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[COPY]](s64), 32
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[EXTRACT]](s32)
+ ; CHECK: %w0 = COPY [[COPY1]](s32)
; CHECK: RET_ReallyLR
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
%2:_(s128) = G_MERGE_VALUES %0, %1
%3:_(s32) = G_EXTRACT %2, 32
+ %w0 = COPY %3
RET_ReallyLR
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir Tue Nov 14 14:42:19 2017
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
@@ -23,19 +24,24 @@ registers:
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
+ ; CHECK-LABEL: name: test_icmp
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x0
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oge), [[COPY]](s64), [[COPY1]]
+ ; CHECK: %w0 = COPY [[FCMP]](s32)
+ ; CHECK: [[FCMP1:%[0-9]+]]:_(s32) = G_FCMP floatpred(uno), [[TRUNC]](s32), [[TRUNC1]]
+ ; CHECK: %w0 = COPY [[FCMP1]](s32)
%0(s64) = COPY %x0
%1(s64) = COPY %x0
%2(s32) = G_TRUNC %0
%3(s32) = G_TRUNC %1
- ; CHECK: [[CMP1:%[0-9]+]]:_(s32) = G_FCMP floatpred(oge), %0(s64), %1
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[CMP1]]
%4(s32) = G_FCMP floatpred(oge), %0, %1
- %6(s1) = G_TRUNC %4(s32)
+ %w0 = COPY %4
- ; CHECK: [[CMP2:%[0-9]+]]:_(s32) = G_FCMP floatpred(uno), %2(s32), %3
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[CMP2]]
%5(s32) = G_FCMP floatpred(uno), %2, %3
- %7(s1) = G_TRUNC %5(s32)
+ %w0 = COPY %5
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir Tue Nov 14 14:42:19 2017
@@ -31,10 +31,12 @@ body: |
bb.0:
liveins: %w0
; CHECK-LABEL: name: test_fptosi_s32_s32
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
- ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- %0:_(s32) = COPY %w0
+ ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[DEF]](s32)
+ ; CHECK: %w0 = COPY [[FPTOSI]](s32)
+ %0:_(s32) = G_IMPLICIT_DEF
%1:_(s32) = G_FPTOSI %0
+ %w0 = COPY %1
...
---
@@ -43,10 +45,12 @@ body: |
bb.0:
liveins: %w0
; CHECK-LABEL: name: test_fptoui_s32_s32
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
- ; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
- %0:_(s32) = COPY %w0
+ ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[DEF]](s32)
+ ; CHECK: %w0 = COPY [[FPTOUI]](s32)
+ %0:_(s32) = G_IMPLICIT_DEF
%1:_(s32) = G_FPTOUI %0
+ %w0 = COPY %1
...
---
@@ -55,10 +59,12 @@ body: |
bb.0:
liveins: %x0
; CHECK-LABEL: name: test_fptosi_s32_s64
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
- ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- %0:_(s64) = COPY %x0
+ ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[DEF]](s32)
+ ; CHECK: %w0 = COPY [[FPTOSI]](s32)
+ %0:_(s32) = G_IMPLICIT_DEF
%1:_(s32) = G_FPTOSI %0
+ %w0 = COPY %1
...
---
@@ -69,8 +75,10 @@ body: |
; CHECK-LABEL: name: test_fptoui_s32_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
+ ; CHECK: %w0 = COPY [[FPTOUI]](s32)
%0:_(s64) = COPY %x0
%1:_(s32) = G_FPTOUI %0
+ %w0 = COPY %1
...
---
@@ -81,8 +89,10 @@ body: |
; CHECK-LABEL: name: test_fptosi_s64_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[FPTOSI:%[0-9]+]]:_(s64) = G_FPTOSI [[COPY]](s32)
+ ; CHECK: %x0 = COPY [[FPTOSI]](s64)
%0:_(s32) = COPY %w0
%1:_(s64) = G_FPTOSI %0
+ %x0 = COPY %1
...
---
@@ -93,8 +103,10 @@ body: |
; CHECK-LABEL: name: test_fptoui_s64_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[FPTOUI:%[0-9]+]]:_(s64) = G_FPTOUI [[COPY]](s32)
+ ; CHECK: %x0 = COPY [[FPTOUI]](s64)
%0:_(s32) = COPY %w0
%1:_(s64) = G_FPTOUI %0
+ %x0 = COPY %1
...
---
@@ -105,8 +117,10 @@ body: |
; CHECK-LABEL: name: test_fptosi_s64_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[FPTOSI:%[0-9]+]]:_(s64) = G_FPTOSI [[COPY]](s64)
+ ; CHECK: %x0 = COPY [[FPTOSI]](s64)
%0:_(s64) = COPY %x0
%1:_(s64) = G_FPTOSI %0
+ %x0 = COPY %1
...
---
@@ -117,8 +131,10 @@ body: |
; CHECK-LABEL: name: test_fptoui_s64_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[FPTOUI:%[0-9]+]]:_(s64) = G_FPTOUI [[COPY]](s64)
+ ; CHECK: %x0 = COPY [[FPTOUI]](s64)
%0:_(s64) = COPY %x0
%1:_(s64) = G_FPTOUI %0
+ %x0 = COPY %1
...
@@ -132,8 +148,10 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[FPTOSI]](s32)
+ ; CHECK: %x0 = COPY [[TRUNC]](s1)
%0:_(s32) = COPY %w0
%1:_(s1) = G_FPTOSI %0
+ %x0 = COPY %1
...
---
@@ -144,9 +162,12 @@ body: |
; CHECK-LABEL: name: test_fptoui_s1_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[FPTOUI]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
+ ; CHECK: %w0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY %w0
%1:_(s1) = G_FPTOUI %0
+ %2:_(s32) = G_ANYEXT %1
+ %w0 = COPY %2
...
---
@@ -157,9 +178,12 @@ body: |
; CHECK-LABEL: name: test_fptosi_s8_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[FPTOSI]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
+ ; CHECK: %w0 = COPY [[COPY1]](s32)
%0:_(s64) = COPY %x0
%1:_(s8) = G_FPTOSI %0
+ %2:_(s32) = G_ANYEXT %1
+ %w0 = COPY %2
...
---
@@ -170,9 +194,12 @@ body: |
; CHECK-LABEL: name: test_fptoui_s8_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[FPTOUI]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
+ ; CHECK: %w0 = COPY [[COPY1]](s32)
%0:_(s64) = COPY %x0
%1:_(s8) = G_FPTOUI %0
+ %2:_(s32) = G_ANYEXT %1
+ %w0 = COPY %2
...
---
@@ -183,9 +210,12 @@ body: |
; CHECK-LABEL: name: test_fptosi_s16_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[FPTOSI]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
+ ; CHECK: %w0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY %w0
%1:_(s16) = G_FPTOSI %0
+ %2:_(s32) = G_ANYEXT %1
+ %w0 = COPY %2
...
---
@@ -196,7 +226,10 @@ body: |
; CHECK-LABEL: name: test_fptoui_s16_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[FPTOUI]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
+ ; CHECK: %w0 = COPY [[COPY1]](s32)
%0:_(s32) = COPY %w0
%1:_(s16) = G_FPTOUI %0
+ %2:_(s32) = G_ANYEXT %1
+ %w0 = COPY %2
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir Tue Nov 14 14:42:19 2017
@@ -122,6 +122,8 @@ body: |
%2:_(s64) = COPY %x2
%3:_(s128) = G_MERGE_VALUES %0, %1
%4:_(s128) = G_INSERT %3, %2, 32
+ %5:_(s64) = G_TRUNC %4
+ %x0 = COPY %5
RET_ReallyLR
...
@@ -140,6 +142,8 @@ body: |
%2:_(s32) = COPY %w2
%3:_(s128) = G_MERGE_VALUES %0, %1
%4:_(s128) = G_INSERT %3, %2, 32
+ %5:_(s64) = G_TRUNC %4
+ %x0 = COPY %5
RET_ReallyLR
...
@@ -151,12 +155,15 @@ body: |
; CHECK-LABEL: name: test_inserts_nonpow2
- ; CHECK: %5:_(s192) = G_MERGE_VALUES %3(s64), %1(s64), %2(s64)
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = COPY %x3
+ ; CHECK: %x0 = COPY [[C]]
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
%2:_(s64) = COPY %x2
%3:_(s64) = COPY %x3
%4:_(s192) = G_MERGE_VALUES %0, %1, %2
%5:_(s192) = G_INSERT %4, %3, 0
+ %6:_(s64), %7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %5
+ %x0 = COPY %6
RET_ReallyLR
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir Tue Nov 14 14:42:19 2017
@@ -35,6 +35,7 @@ body: |
; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s32)
%0:_(s32) = COPY %w0
%1:_(s32) = G_SITOFP %0
+ %w0 = COPY %1
...
---
@@ -47,6 +48,7 @@ body: |
; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY]](s32)
%0:_(s32) = COPY %w0
%1:_(s32) = G_UITOFP %0
+ %w0 = COPY %1
...
---
@@ -59,6 +61,7 @@ body: |
; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[COPY]](s64)
%0:_(s64) = COPY %x0
%1:_(s32) = G_SITOFP %0
+ %w0 = COPY %1
...
---
@@ -71,6 +74,7 @@ body: |
; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[COPY]](s64)
%0:_(s64) = COPY %x0
%1:_(s32) = G_UITOFP %0
+ %w0 = COPY %1
...
---
@@ -83,6 +87,7 @@ body: |
; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32)
%0:_(s32) = COPY %w0
%1:_(s64) = G_SITOFP %0
+ %w0 = COPY %1
...
---
@@ -95,6 +100,7 @@ body: |
; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[COPY]](s32)
%0:_(s32) = COPY %w0
%1:_(s64) = G_UITOFP %0
+ %x0 = COPY %1
...
---
@@ -107,6 +113,7 @@ body: |
; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s64)
%0:_(s64) = COPY %x0
%1:_(s64) = G_SITOFP %0
+ %x0 = COPY %1
...
---
@@ -119,6 +126,7 @@ body: |
; CHECK: [[UITOFP:%[0-9]+]]:_(s64) = G_UITOFP [[COPY]](s64)
%0:_(s64) = COPY %x0
%1:_(s64) = G_UITOFP %0
+ %x0 = COPY %1
...
@@ -137,6 +145,7 @@ body: |
%0:_(s32) = COPY %w0
%1:_(s1) = G_TRUNC %0
%2:_(s32) = G_SITOFP %1
+ %w0 = COPY %2
...
---
@@ -153,6 +162,7 @@ body: |
%0:_(s32) = COPY %w0
%1:_(s1) = G_TRUNC %0
%2:_(s32) = G_UITOFP %1
+ %w0 = COPY %2
...
---
@@ -170,6 +180,7 @@ body: |
%0:_(s32) = COPY %w0
%1:_(s8) = G_TRUNC %0
%2:_(s64) = G_SITOFP %1
+ %x0 = COPY %2
...
---
@@ -186,6 +197,7 @@ body: |
%0:_(s32) = COPY %w0
%1:_(s8) = G_TRUNC %0
%2:_(s64) = G_UITOFP %1
+ %x0 = COPY %2
...
---
@@ -203,6 +215,7 @@ body: |
%0:_(s32) = COPY %w0
%1:_(s16) = G_TRUNC %0
%2:_(s32) = G_SITOFP %1
+ %w0 = COPY %2
...
---
@@ -219,4 +232,5 @@ body: |
%0:_(s32) = COPY %w0
%1:_(s16) = G_TRUNC %0
%2:_(s32) = G_UITOFP %1
+ %w0 = COPY %2
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir Tue Nov 14 14:42:19 2017
@@ -31,27 +31,36 @@ body: |
; CHECK-LABEL: name: test_load
%0(p0) = COPY %x0
- ; CHECK: [[BIT8:%[0-9]+]]:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr)
- ; CHECK: %1:_(s1) = G_TRUNC [[BIT8]]
%1(s1) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %9:_(s32) = G_ANYEXT %1
+ %w0 = COPY %9
; CHECK: %2:_(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr)
%2(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %10:_(s32) = G_ANYEXT %2
+ %w0 = COPY %10
; CHECK: %3:_(s16) = G_LOAD %0(p0) :: (load 2 from %ir.addr)
%3(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
+ %11:_(s32) = G_ANYEXT %3
+ %w0 = COPY %11
; CHECK: %4:_(s32) = G_LOAD %0(p0) :: (load 4 from %ir.addr)
%4(s32) = G_LOAD %0 :: (load 4 from %ir.addr)
+ %w0 = COPY %4
; CHECK: %5:_(s64) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
%5(s64) = G_LOAD %0 :: (load 8 from %ir.addr)
+ %x0 = COPY %5
- ; CHECK: %6:_(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
%6(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
+ %12:_(s64) = G_PTRTOINT %6
+ %x0 = COPY %12
; CHECK: %7:_(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
%7(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
+ %13:_(s64) = G_BITCAST %7
+ %x0 = COPY %13
; CHECK: [[LOAD0:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load 16 from %ir.addr)
; CHECK: [[OFFSET1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
@@ -59,6 +68,8 @@ body: |
; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP1]](p0) :: (load 16 from %ir.addr)
; CHECK: %8:_(s128) = G_MERGE_VALUES [[LOAD0]](s64), [[LOAD1]](s64)
%8(s128) = G_LOAD %0(p0) :: (load 16 from %ir.addr)
+ %14:_(s64) = G_TRUNC %8
+ %x0 = COPY %14
...
---
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir Tue Nov 14 14:42:19 2017
@@ -30,8 +30,7 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[TRUNC]], [[TRUNC1]]
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[MUL]](s32)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC2]](s8)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[MUL]](s32)
; CHECK: %x0 = COPY [[ANYEXT]](s64)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
@@ -56,9 +55,14 @@ body: |
; CHECK: [[SMULH:%[0-9]+]]:_(s64) = G_SMULH [[COPY]], [[COPY1]]
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[SMULH]](s64), [[C]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK: %x0 = COPY [[MUL]](s64)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+ ; CHECK: %w0 = COPY [[COPY2]](s32)
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
%2:_(s64), %3:_(s1) = G_SMULO %0, %1
+ %x0 = COPY %2
+ %4:_(s32) = G_ANYEXT %3
+ %w0 = COPY %4
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir Tue Nov 14 14:42:19 2017
@@ -22,9 +22,15 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY %w2
- ; CHECK: [[MV:%[0-9]+]]:_(<3 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32)
+ ; CHECK: %w0 = COPY [[COPY]](s32)
+ ; CHECK: %w1 = COPY [[COPY1]](s32)
+ ; CHECK: %w2 = COPY [[COPY2]](s32)
%0(s32) = COPY %w0
%1(s32) = COPY %w1
%2(s32) = COPY %w2
%3(<3 x s32>) = G_MERGE_VALUES %0(s32), %1(s32), %2(s32)
+ %4:_(s32), %5:_(s32), %6:_(s32) = G_UNMERGE_VALUES %3
+ %w0 = COPY %4
+ %w1 = COPY %5
+ %w2 = COPY %6
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir Tue Nov 14 14:42:19 2017
@@ -3,17 +3,9 @@
---
name: test_scalar_or_small
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
body: |
bb.0:
liveins: %x0, %x1, %x2, %x3
-
; CHECK-LABEL: name: test_scalar_or_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
@@ -21,29 +13,17 @@ body: |
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[TRUNC]], [[TRUNC1]]
; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR]](s32)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC2]](s8)
- ; CHECK: %x0 = COPY [[ANYEXT]](s64)
- %0(s64) = COPY %x0
- %1(s64) = COPY %x1
- %2(s8) = G_TRUNC %0
- %3(s8) = G_TRUNC %1
- %4(s8) = G_OR %2, %3
- %5(s64) = G_ANYEXT %4
- %x0 = COPY %5
+ ; CHECK: %x0 = COPY [[TRUNC2]](s8)
+ %0:_(s64) = COPY %x0
+ %1:_(s64) = COPY %x1
+ %2:_(s8) = G_TRUNC %0
+ %3:_(s8) = G_TRUNC %1
+ %4:_(s8) = G_OR %2, %3
+ %x0 = COPY %4
...
---
name: test_big_scalar_power_of_2
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
- - { id: 6, class: _ }
- - { id: 7, class: _ }
- - { id: 8, class: _ }
body: |
bb.0:
liveins: %x0, %x1, %x2, %x3
@@ -61,14 +41,14 @@ body: |
; CHECK: %x0 = COPY [[OR]](s64)
; CHECK: %x1 = COPY [[OR1]](s64)
; CHECK: RET_ReallyLR implicit %x0, implicit %x1
- %0(s64) = COPY %x0
- %1(s64) = COPY %x1
- %2(s64) = COPY %x2
- %3(s64) = COPY %x3
- %4(s128) = G_MERGE_VALUES %0, %1
- %5(s128) = G_MERGE_VALUES %2, %3
- %6(s128) = G_OR %4, %5
- %7(s64), %8(s64) = G_UNMERGE_VALUES %6
+ %0:_(s64) = COPY %x0
+ %1:_(s64) = COPY %x1
+ %2:_(s64) = COPY %x2
+ %3:_(s64) = COPY %x3
+ %4:_(s128) = G_MERGE_VALUES %0, %1
+ %5:_(s128) = G_MERGE_VALUES %2, %3
+ %6:_(s128) = G_OR %4, %5
+ %7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %6
%x0 = COPY %7
%x1 = COPY %8
RET_ReallyLR implicit %x0, implicit %x1
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir Tue Nov 14 14:42:19 2017
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-unknown-unknown -global-isel -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s
--- |
; ModuleID = '/tmp/test.ll'
@@ -62,21 +63,39 @@ registers:
- { id: 10, class: _, preferred-register: '' }
liveins:
body: |
+ ; CHECK-LABEL: name: legalize_phi
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: %w0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.3(0x80000000)
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+ ; CHECK: G_BR %bb.3
+ ; CHECK: bb.2:
+ ; CHECK: successors: %bb.3(0x80000000)
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
+ ; CHECK: bb.3:
+ ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC2]](s16), %bb.2
+ ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
+ ; CHECK: %w0 = COPY [[AND]](s32)
+ ; CHECK: RET_ReallyLR implicit %w0
bb.0:
; Test that we insert legalization artifacts(Truncs here) into the correct BBs
; while legalizing the G_PHI to s16.
- ; CHECK-LABEL: name: legalize_phi
- ; CHECK-LABEL: bb.1:
- ; CHECK: [[ADD_BB1:%.*]]:_(s32) = G_ADD
- ; CHECK: [[RES_BB1:%.*]]:_(s16) = G_TRUNC [[ADD_BB1]]
-
- ; CHECK-LABEL: bb.2:
- ; CHECK: [[ADD_BB2:%.*]]:_(s32) = G_ADD
- ; CHECK: [[RES_BB2:%.*]]:_(s16) = G_TRUNC [[ADD_BB2]]
-
- ; CHECK-LABEL: bb.3:
- ; CHECK: [[RES_PHI:%.*]]:_(s16) = G_PHI [[RES_BB1]](s16), %bb.1, [[RES_BB2]](s16), %bb.2
- ; CHECK: [[RES:%.*]]:_(s1) = G_TRUNC [[RES_PHI]]
+
+
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: %w0
@@ -125,18 +144,24 @@ registers:
- { id: 5, class: _, preferred-register: '' }
liveins:
body: |
+ ; CHECK-LABEL: name: legalize_phi_ptr
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: %w2, %x0, %x1
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY %x1
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY %w2
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY2]](s32)
+ ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x80000000)
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI:%[0-9]+]]:_(p0) = G_PHI [[COPY]](p0), %bb.0, [[COPY1]](p0), %bb.1
+ ; CHECK: %x0 = COPY [[PHI]](p0)
+ ; CHECK: RET_ReallyLR implicit %x0
bb.1:
- ; CHECK-LABEL: name: legalize_phi_ptr
- ; CHECK-LABEL: bb.0:
- ; CHECK: [[A:%[0-9]+]]:_(p0) = COPY %x0
- ; CHECK: [[B:%[0-9]+]]:_(p0) = COPY %x1
- ; CHECK: [[CE:%[0-9]+]]:_(s32) = COPY %w2
- ; CHECK: [[C:%[0-9]+]]:_(s1) = G_TRUNC [[CE]]
-
- ; CHECK-LABEL: bb.1:
- ; CHECK-LABEL: bb.2:
- ; CHECK: %3:_(p0) = G_PHI [[A]](p0), %bb.0, [[B]](p0), %bb.1
- ; CHECK: %x0 = COPY %3(p0)
+
successors: %bb.2, %bb.3
liveins: %w2, %x0, %x1
@@ -178,23 +203,41 @@ registers:
- { id: 10, class: _, preferred-register: '' }
liveins:
body: |
+ ; CHECK-LABEL: name: legalize_phi_empty
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: %w0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
+ ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.3(0x80000000)
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
+ ; CHECK: G_BR %bb.3
+ ; CHECK: bb.2:
+ ; CHECK: successors: %bb.3(0x80000000)
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+ ; CHECK: bb.3:
+ ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC2]](s16), %bb.2
+ ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C3]]
+ ; CHECK: %w0 = COPY [[AND]](s32)
+ ; CHECK: RET_ReallyLR implicit %w0
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: %w0
; Test that we properly legalize a phi with a predecessor that's empty
- ; CHECK-LABEL: name: legalize_phi_empty
- ; CHECK-LABEL: bb.0:
- ; CHECK: [[ENTRY_ADD:%.*]]:_(s32) = G_ADD
-
- ; CHECK-LABEL: bb.1:
- ; CHECK: [[ADD_BB1:%.*]]:_(s32) = G_ADD
- ; CHECK: [[RES_BB1:%.*]]:_(s16) = G_TRUNC [[ADD_BB1]]
- ; CHECK-LABEL: bb.2:
- ; CHECK: [[RES_BB2:%.*]]:_(s16) = G_TRUNC [[ENTRY_ADD]]
- ; CHECK: [[RES_PHI:%.*]]:_(s16) = G_PHI [[RES_BB1]](s16), %bb.1, [[RES_BB2]](s16), %bb.2
- ; CHECK: [[RES:%.*]]:_(s1) = G_TRUNC [[RES_PHI]]
+
%0(s32) = COPY %w0
%1(s32) = G_CONSTANT i32 0
@@ -243,19 +286,39 @@ registers:
- { id: 7, class: _, preferred-register: '' }
liveins:
body: |
+ ; CHECK-LABEL: name: legalize_phi_loop
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: %w0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC]](s16), %bb.0, %14(s16), %bb.1
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT]], [[COPY1]]
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[ADD]](s32)
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]]
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+ ; CHECK: G_BRCOND [[TRUNC2]](s1), %bb.1
+ ; CHECK: bb.2:
+ ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; CHECK: %w0 = COPY [[AND1]](s32)
+ ; CHECK: RET_ReallyLR implicit %w0
bb.0:
successors: %bb.1(0x80000000)
liveins: %w0
; Test that we properly legalize a phi that uses a value from the same BB
- ; CHECK-LABEL: name: legalize_phi_loop
- ; CHECK-LABEL: bb.0:
- ; CHECK: [[C0:%.*]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[RES_BB1:%.*]]:_(s16) = G_TRUNC [[C0]]
-
- ; CHECK-LABEL: bb.1:
- ; CHECK: [[RES_PHI:%.*]]:_(s16) = G_PHI [[RES_BB1]](s16), %bb.0, [[RES_BB2:%.*]](s16), %bb.1
- ; CHECK-NEXT: G_ANYEXT [[RES_PHI]]
- ; CHECK: [[RES_BB2]]:_(s16) = G_ANYEXT
+
%0(s32) = COPY %w0
%2(s8) = G_CONSTANT i8 1
%7(s8) = G_CONSTANT i8 0
@@ -291,19 +354,32 @@ registers:
- { id: 4, class: _, preferred-register: '' }
liveins:
body: |
+ ; CHECK-LABEL: name: legalize_phi_cycle
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: %w0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC]](s16), %bb.0, %8(s16), %bb.1
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[PHI]](s16)
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[AND]](s32), [[COPY]]
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[PHI]](s16)
+ ; CHECK: G_BRCOND [[TRUNC2]](s1), %bb.1
+ ; CHECK: bb.2:
+ ; CHECK: %w0 = COPY [[AND]](s32)
+ ; CHECK: RET_ReallyLR implicit %w0
bb.0:
successors: %bb.1(0x80000000)
liveins: %w0
; Test that we properly legalize a phi that uses itself
- ; CHECK-LABEL: name: legalize_phi_cycle
- ; CHECK-LABEL: bb.0:
- ; CHECK: [[C0:%.*]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[RES_BB1:%.*]]:_(s16) = G_TRUNC [[C0]]
-
- ; CHECK-LABEL: bb.1:
- ; CHECK: [[RES_PHI:%.*]]:_(s16) = G_PHI [[RES_BB1]](s16), %bb.0, [[RES_BB2:%.*]](s16), %bb.1
- ; CHECK-NEXT: G_TRUNC
- ; CHECK: [[RES_BB2]]:_(s16) = COPY
+
%0(s32) = COPY %w0
%4(s8) = G_CONSTANT i8 0
@@ -347,30 +423,50 @@ registers:
- { id: 14, class: _, preferred-register: '' }
liveins:
body: |
+ ; CHECK-LABEL: name: legalize_phi_same_bb
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: %w0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
+ ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.3(0x80000000)
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]]
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
+ ; CHECK: G_BR %bb.3
+ ; CHECK: bb.2:
+ ; CHECK: successors: %bb.3(0x80000000)
+ ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[C3]](s32)
+ ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+ ; CHECK: bb.3:
+ ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC2]](s16), %bb.1, [[TRUNC4]](s16), %bb.2
+ ; CHECK: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC3]](s16), %bb.2
+ ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C4]]
+ ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ANYEXT1]], [[C5]]
+ ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[C]]1, [[C]]2
+ ; CHECK: %w0 = COPY [[C]]3(s32)
+ ; CHECK: RET_ReallyLR implicit %w0
bb.0:
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: %w0
; Make sure that we correctly insert the new legalized G_PHI at the
; correct location (ie make sure G_PHIs are the first insts in the BB).
- ; CHECK-LABEL: name: legalize_phi_same_bb
- ; CHECK-LABEL: bb.0:
- ; CHECK: [[C42:%.*]]:_(s32) = G_CONSTANT i32 42
- ; CHECK: [[ENTRY_ADD:%.*]]:_(s32) = G_ADD
-
- ; CHECK-LABEL: bb.1:
- ; CHECK: [[BB1_ADD:%.*]]:_(s32) = G_ADD
- ; CHECK: [[RES1_BB1:%.*]]:_(s16) = G_TRUNC [[BB1_ADD]]
- ; CHECK: [[RES2_BB1:%.*]]:_(s16) = G_TRUNC [[BB1_ADD]]
-
- ; CHECK-LABEL: bb.2:
- ; CHECK: [[RES1_BB2:%.*]]:_(s16) = G_TRUNC [[ENTRY_ADD]]
- ; CHECK: [[RES2_BB2:%.*]]:_(s16) = G_TRUNC [[C42]]
-
- ; CHECK-LABEL: bb.3:
- ; CHECK: [[RES1_PHI:%.*]]:_(s16) = G_PHI [[RES1_BB1]](s16), %bb.1, [[RES1_BB2]](s16), %bb.2
- ; CHECK-NEXT: [[RES_PHI:%.*]]:_(s16) = G_PHI [[RES2_BB1]](s16), %bb.1, [[RES2_BB2]](s16), %bb.2
- ; CHECK-NEXT: G_TRUNC
- ; CHECK-NEXT: G_TRUNC
+
+
+
%0(s32) = COPY %w0
%1(s32) = G_CONSTANT i32 0
@@ -431,27 +527,51 @@ registers:
- { id: 15, class: _, preferred-register: '' }
liveins:
body: |
+ ; CHECK-LABEL: name: legalize_phi_diff_bb
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK: liveins: %w0, %w1
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %w0
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 44
+ ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 43
+ ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[C]]
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s32)
+ ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
+ ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
+ ; CHECK: G_BR %bb.2
+ ; CHECK: bb.1:
+ ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK: [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC2]](s16), %bb.0, [[C]]2(s16), %bb.1
+ ; CHECK: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[PHI]](s16)
+ ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI]](s16)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C5]]
+ ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[C2]]
+ ; CHECK: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ADD1]](s32), [[C3]]
+ ; CHECK: [[TRUNC4:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP1]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[PHI]](s16)
+ ; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32)
+ ; CHECK: G_BRCOND [[TRUNC4]](s1), %bb.2
+ ; CHECK: G_BR %bb.1
+ ; CHECK: bb.2:
+ ; CHECK: [[PHI1:%[0-9]+]]:_(s16) = G_PHI [[COPY1]](s16), %bb.1, [[TRUNC1]](s16), %bb.0
+ ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[C]]8, [[C]]7
+ ; CHECK: %w0 = COPY [[AND1]](s32)
+ ; CHECK: RET_ReallyLR implicit %w0
bb.0:
successors: %bb.1(0x40000000), %bb.3(0x40000000)
liveins: %w0, %w1
; Make sure that we correctly legalize PHIs sharing common defs
; in different BBs.
- ; CHECK-LABEL: name: legalize_phi_diff_bb
- ; CHECK-LABEL: bb.0:
- ; CHECK: [[C44:%.*]]:_(s32) = G_CONSTANT i32 44
- ; CHECK: [[C43:%.*]]:_(s32) = G_CONSTANT i32 43
- ; CHECK: [[ENTRY_ADD:%.*]]:_(s32) = G_ADD
- ; CHECK: [[RES_ENTRY:%.*]]:_(s16) = G_TRUNC [[ENTRY_ADD]]
- ; CHECK: [[RES_ENTRY1:%.*]]:_(s16) = G_TRUNC [[ENTRY_ADD]]
-
- ; CHECK-LABEL: bb.1:
- ; CHECK: [[RES1_PHI:%.*]]:_(s16) = G_PHI [[RES_ENTRY]](s16), %bb.0, [[RES_BB1:%.*]](s16), %bb.1
- ; CHECK: [[RES_BB1:%.*]]:_(s16) = G_TRUNC
- ; CHECK: [[RES_FOR_BB2:%.*]]:_(s16) = COPY [[RES1_PHI]]
-
- ; CHECK-LABEL: bb.2:
- ; CHECK: [[RES2_PHI:%.*]]:_(s16) = G_PHI [[RES_FOR_BB2]](s16), %bb.1, [[RES_ENTRY1:%.*]](s16), %bb.0
- ; CHECK-NEXT: G_TRUNC
+
+
%0(s32) = COPY %w0
%1(s32) = COPY %w1
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir Tue Nov 14 14:42:19 2017
@@ -28,11 +28,13 @@ body: |
; CHECK: BL $pow, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit-def %d0
; CHECK: %4:_(s64) = COPY %d0
%4:_(s64) = G_FPOW %0, %1
+ %x0 = COPY %4
; CHECK: %s0 = COPY %2
; CHECK: %s1 = COPY %3
; CHECK: BL $powf, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %s1, implicit-def %s0
; CHECK: %5:_(s32) = COPY %s0
%5:_(s32) = G_FPOW %2, %3
+ %w0 = COPY %5
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir Tue Nov 14 14:42:19 2017
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
@@ -32,12 +33,16 @@ body: |
liveins: %x0, %x1, %x2, %x3
; CHECK-LABEL: name: test_urem_64
- ; CHECK: [[QUOT:%[0-9]+]]:_(s64) = G_UDIV %0, %1
- ; CHECK: [[PROD:%[0-9]+]]:_(s64) = G_MUL [[QUOT]], %1
- ; CHECK: [[RES:%[0-9]+]]:_(s64) = G_SUB %0, [[PROD]]
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+ ; CHECK: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]]
+ ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[UDIV]], [[COPY1]]
+ ; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[MUL]]
+ ; CHECK: %x0 = COPY [[SUB]](s64)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
%2(s64) = G_UREM %0, %1
+ %x0 = COPY %2
...
@@ -52,18 +57,22 @@ registers:
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
- ; CHECK-LABEL: name: test_srem_32
- ; CHECK: [[T1:%.*]]:_(s32) = G_TRUNC %0(s64)
- ; CHECK: [[T2:%.*]]:_(s32) = G_TRUNC %1(s64)
- ; CHECK: [[DIV:%.*]]:_(s32) = G_SDIV [[T1]], [[T2]]
- ; CHECK: [[MUL:%.*]]:_(s32) = G_MUL [[DIV]], [[T2]]
- ; CHECK: [[RES:%.*]]:_(s32) = G_SUB [[T1]], [[MUL]]
+ ; CHECK-LABEL: name: test_srem_32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[TRUNC]], [[TRUNC1]]
+ ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[TRUNC1]]
+ ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[MUL]]
+ ; CHECK: %w0 = COPY [[SUB]](s32)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
%3(s32) = G_TRUNC %0
%4(s32) = G_TRUNC %1
%5(s32) = G_SREM %3, %4
+ %w0 = COPY %5
...
---
@@ -77,30 +86,35 @@ registers:
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
- ; CHECK-LABEL: name: test_srem_8
- ; CHECK: [[C1:%.*]]:_(s32) = G_CONSTANT i32 24
- ; CHECK: [[SRC1:%.*]]:_(s32) = G_TRUNC %0(s64)
- ; CHECK: [[SHL1:%.*]]:_(s32) = G_SHL [[SRC1]], [[C1]]
- ; CHECK: [[LHS_SEXT:%.*]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
- ; CHECK: [[C2:%.*]]:_(s32) = G_CONSTANT i32 24
- ; CHECK: [[SRC2:%.*]]:_(s32) = G_TRUNC %1(s64)
- ; CHECK: [[SHL2:%.*]]:_(s32) = G_SHL [[SRC2]], [[C2]]
- ; CHECK: [[RHS_SEXT:%.*]]:_(s32) = G_ASHR [[SHL2]], [[C2]]
- ; CHECK: [[SDIV:%.*]]:_(s32) = G_SDIV [[LHS_SEXT]], [[RHS_SEXT]]
- ; CHECK: [[A:%.*]]:_(s32) = COPY [[SDIV]]
- ; CHECK: [[SRC3:%.*]]:_(s32) = G_TRUNC %1(s64)
- ; CHECK: [[MUL:%.*]]:_(s32) = G_MUL [[A]], [[SRC3]]
- ; CHECK: [[SRC4:%.*]]:_(s32) = G_TRUNC %0(s64)
- ; CHECK: [[SRC5:%.*]]:_(s32) = COPY [[MUL]]
- ; CHECK: [[SUB:%.*]]:_(s32) = G_SUB [[SRC4]], [[SRC5]]
- ; CHECK: [[RES:%.*]]:_(s8) = G_TRUNC [[SUB]]
+ ; CHECK-LABEL: name: test_srem_8
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]]
+ ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]]
+ ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
+ ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SDIV]](s32)
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY2]], [[TRUNC2]]
+ ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[MUL]](s32)
+ ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC3]], [[COPY3]]
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
+ ; CHECK: %w0 = COPY [[COPY4]](s32)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
%6(s8) = G_TRUNC %0
%7(s8) = G_TRUNC %1
%8(s8) = G_SREM %6, %7
+ %9:_(s32) = G_ANYEXT %8
+ %w0 = COPY %9
...
---
name: test_frem
@@ -114,20 +128,32 @@ registers:
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
- ; CHECK-LABEL: name: test_frem
- ; CHECK: %d0 = COPY %0
- ; CHECK: %d1 = COPY %1
+ ; CHECK-LABEL: name: test_frem
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+ ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def %sp, implicit %sp
+ ; CHECK: %d0 = COPY [[COPY]](s64)
+ ; CHECK: %d1 = COPY [[COPY1]](s64)
; CHECK: BL $fmod, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %d0, implicit %d1, implicit-def %d0
- ; CHECK: [[RES:%.*]]:_(s64) = COPY %d0
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY %d0
+ ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def %sp, implicit %sp
+ ; CHECK: %x0 = COPY [[COPY2]](s64)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def %sp, implicit %sp
+ ; CHECK: %s0 = COPY [[TRUNC]](s32)
+ ; CHECK: %s1 = COPY [[TRUNC1]](s32)
+ ; CHECK: BL $fmodf, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %s1, implicit-def %s0
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY %s0
+ ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def %sp, implicit %sp
+ ; CHECK: %w0 = COPY [[COPY3]](s32)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
%2(s64) = G_FREM %0, %1
+ %x0 = COPY %2
- ; CHECK: %s0 = COPY %3
- ; CHECK: %s1 = COPY %4
- ; CHECK: BL $fmodf, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %s1, implicit-def %s0
- ; CHECK: [[RES:%.*]]:_(s32) = COPY %s0
%3(s32) = G_TRUNC %0
%4(s32) = G_TRUNC %1
%5(s32) = G_FREM %3, %4
+ %w0 = COPY %5
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir Tue Nov 14 14:42:19 2017
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
@@ -22,37 +23,49 @@ registers:
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
+ ; CHECK-LABEL: name: test_shift
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]]
+ ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]]
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]]
+ ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
+ ; CHECK: [[ASHR2:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[ASHR1]]
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ASHR2]](s32)
+ ; CHECK: %w0 = COPY [[COPY2]](s32)
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC2]], [[C2]]
+ ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC3]], [[C3]]
+ ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[AND1]]
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+ ; CHECK: %w0 = COPY [[COPY3]](s32)
+ ; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
+ ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY1]]0, [[COPY1]]1
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]]2(s32)
+ ; CHECK: %w0 = COPY [[COPY4]](s32)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
- ; CHECK: [[C1:%.*]]:_(s32) = G_CONSTANT i32 24
- ; CHECK: [[SRC:%.*]]:_(s32) = G_TRUNC %0(s64)
- ; CHECK: [[SHL1:%.*]]:_(s32) = G_SHL [[SRC]], [[C1]]
- ; CHECK: [[SEXT1:%.*]]:_(s32) = G_ASHR [[SHL1]], [[C1]]
- ; CHECK: [[C2:%.*]]:_(s32) = G_CONSTANT i32 24
- ; CHECK: [[SRC2:%.*]]:_(s32) = G_TRUNC %1(s64)
- ; CHECK: [[SHL2:%.*]]:_(s32) = G_SHL [[SRC2]], [[C2]]
- ; CHECK: [[SEXT2:%.*]]:_(s32) = G_ASHR [[SHL2]], [[C2]]
- ; CHECK: [[RES32:%[0-9]+]]:_(s32) = G_ASHR [[SEXT1]], [[SEXT2]]
- ; CHECK: %4:_(s8) = G_TRUNC [[RES32]]
%4(s8) = G_ASHR %2, %3
+ %7:_(s32) = G_ANYEXT %4
+ %w0 = COPY %7
- ; CHECK: [[C1:%.*]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[SRC:%.*]]:_(s32) = G_TRUNC %0(s64)
- ; CHECK: [[ZEXT:%.*]]:_(s32) = G_AND [[SRC]], [[C1]]
- ; CHECK: [[C2:%.*]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[SRC2:%.*]]:_(s32) = G_TRUNC %1(s64)
- ; CHECK: [[ZEXT2:%.*]]:_(s32) = G_AND [[SRC2]], [[C2]]
- ; CHECK: [[RES32:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT]], [[ZEXT2]]
- ; CHECK: %5:_(s8) = G_TRUNC [[RES32]]
%5(s8) = G_LSHR %2, %3
+ %8:_(s32) = G_ANYEXT %5
+ %w0 = COPY %8
- ; CHECK: [[OP0:%.*]]:_(s32) = G_TRUNC %0
- ; CHECK: [[OP1:%.*]]:_(s32) = G_TRUNC %1
- ; CHECK: [[RES32:%.*]]:_(s32) = G_SHL [[OP0]], [[OP1]]
- ; CHECK: [[RES:%.*]]:_(s8) = G_TRUNC [[RES32]](s32)
%6(s8) = G_SHL %2, %3
+ %9:_(s32) = G_ANYEXT %6
+ %w0 = COPY %9
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir Tue Nov 14 14:42:19 2017
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
@@ -12,6 +13,9 @@
define void @bitcast128() {
ret void
}
+ define void @testExtOfCopyOfTrunc() {
+ ret void
+ }
...
---
@@ -35,6 +39,46 @@ registers:
- { id: 15, class: _ }
- { id: 16, class: _ }
body: |
+ ; CHECK-LABEL: name: test_simple
+ ; CHECK: bb.0.entry:
+ ; CHECK: successors: %bb.1.next(0x80000000)
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[COPY]](s64)
+ ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[INTTOPTR]](p0)
+ ; CHECK: %x0 = COPY [[PTRTOINT]](s64)
+ ; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1.next
+ ; CHECK: bb.1.next:
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC2]], [[TRUNC3]]
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
+ ; CHECK: %w0 = COPY [[COPY1]](s32)
+ ; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC4]], [[TRUNC5]]
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
+ ; CHECK: %w0 = COPY [[COPY2]](s32)
+ ; CHECK: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC6]], [[TRUNC7]]
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SELECT2]](s32)
+ ; CHECK: %w0 = COPY [[COPY3]](s32)
+ ; CHECK: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC1]], [[TRUNC1]]
+ ; CHECK: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[TRUNC]](s1), [[COPY]], [[COPY]]
+ ; CHECK: %x0 = COPY [[SELECT4]](s64)
+ ; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[COPY]](s64)
+ ; CHECK: [[BITCAST1:%[0-9]+]]:_(s64) = G_BITCAST [[TRUNC]]2(<2 x s32>)
+ ; CHECK: %x0 = COPY [[BITCAST1]](s64)
+ ; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[TRUNC]]0(s32)
+ ; CHECK: %w0 = COPY [[TRUNC]]4(s32)
+ ; CHECK: [[BITCAST3:%[0-9]+]]:_(<4 x s8>) = G_BITCAST [[COPY]](s64)
+ ; CHECK: [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[TRUNC]]5(<4 x s8>)
+ ; CHECK: %w0 = COPY [[BITCAST4]](s32)
+ ; CHECK: [[BITCAST5:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[COPY]](s64)
+ ; CHECK: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[TRUNC]]6(<2 x s16>)
+ ; CHECK: %w0 = COPY [[BITCAST6]](s32)
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
%0(s64) = COPY %x0
@@ -44,48 +88,41 @@ body: |
%3(s16) = G_TRUNC %0
%4(s32) = G_TRUNC %0
- ; CHECK-LABEL: name: test_simple
- ; CHECK: %5:_(p0) = G_INTTOPTR %0
- ; CHECK: %6:_(s64) = G_PTRTOINT %5
%5(p0) = G_INTTOPTR %0
%6(s64) = G_PTRTOINT %5
+ %x0 = COPY %6
- ; CHECK: G_BRCOND %1(s1), %bb.1.next
G_BRCOND %1, %bb.1.next
bb.1.next:
- ; CHECK: [[LHS:%[0-9]+]]:_(s32) = G_TRUNC %0
- ; CHECK: [[RHS:%[0-9]+]]:_(s32) = G_TRUNC %0
- ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SELECT %1(s1), [[LHS]], [[RHS]]
- ; CHECK: %7:_(s1) = G_TRUNC [[RES]](s32)
%7(s1) = G_SELECT %1, %1, %1
+ %21:_(s32) = G_ANYEXT %7
+ %w0 = COPY %21
- ; CHECK: [[LHS:%[0-9]+]]:_(s32) = G_TRUNC %0
- ; CHECK: [[RHS:%[0-9]+]]:_(s32) = G_TRUNC %0
- ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SELECT %1(s1), [[LHS]], [[RHS]]
- ; CHECK: %8:_(s8) = G_TRUNC [[RES]](s32)
%8(s8) = G_SELECT %1, %2, %2
+ %20:_(s32) = G_ANYEXT %8
+ %w0 = COPY %20
- ; CHECK: [[LHS:%[0-9]+]]:_(s32) = G_TRUNC %0
- ; CHECK: [[RHS:%[0-9]+]]:_(s32) = G_TRUNC %0
- ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SELECT %1(s1), [[LHS]], [[RHS]]
- ; CHECK: %9:_(s16) = G_TRUNC [[RES]](s32)
%9(s16) = G_SELECT %1, %3, %3
+ %19:_(s32) = G_ANYEXT %9
+ %w0 = COPY %19
%10(s32) = G_SELECT %1, %4, %4
%11(s64) = G_SELECT %1, %0, %0
+ %x0 = COPY %11
- ; CHECK: %12:_(<2 x s32>) = G_BITCAST %0
- ; CHECK: %13:_(s64) = G_BITCAST %12
- ; CHECK: %14:_(s32) = G_BITCAST %10
- ; CHECK: %15:_(<4 x s8>) = G_BITCAST %0
- ; CHECK: %16:_(<2 x s16>) = G_BITCAST %0
%12(<2 x s32>) = G_BITCAST %0
%13(s64) = G_BITCAST %12
+ %x0 = COPY %13
%14(s32) = G_BITCAST %10
+ %w0 = COPY %14
%15(<4 x s8>) = G_BITCAST %0
+ %17:_(s32) = G_BITCAST %15
+ %w0 = COPY %17
%16(<2 x s16>) = G_BITCAST %0
+ %18:_(s32) = G_BITCAST %16
+ %w0 = COPY %18
...
---
@@ -99,9 +136,15 @@ registers:
body: |
bb.1:
liveins: %x0, %x1
- ; CHECK-LABEL: bitcast128
; This is legal and shouldn't be changed.
- ; CHECK: %2:_(<2 x s64>) = G_BITCAST %3(s128)
+ ; CHECK-LABEL: name: bitcast128
+ ; CHECK: liveins: %x0, %x1
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %x1
+ ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
+ ; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[MV]](s128)
+ ; CHECK: %q0 = COPY [[BITCAST]](<2 x s64>)
+ ; CHECK: RET_ReallyLR implicit %q0
%0(s64) = COPY %x0
%1(s64) = COPY %x1
%3(s128) = G_MERGE_VALUES %0(s64), %1(s64)
@@ -110,3 +153,29 @@ body: |
RET_ReallyLR implicit %q0
...
+---
+name: testExtOfCopyOfTrunc
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _}
+ - { id: 1, class: _}
+ - { id: 2, class: _}
+ - { id: 3, class: _}
+body: |
+ bb.1:
+ liveins: %x0
+ ; CHECK-LABEL: name: testExtOfCopyOfTrunc
+ ; CHECK: liveins: %x0
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %x0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s1) = COPY %1:_(s1)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
+ ; CHECK: %x0 = COPY [[COPY2]](s64)
+ ; CHECK: RET_ReallyLR implicit %x0
+ %0(s64) = COPY %x0
+ %1(s1) = G_TRUNC %0
+ %2(s1) = COPY %1
+ %3(s64) = G_ANYEXT %2
+ %x0 = COPY %3
+ RET_ReallyLR implicit %x0
+
+...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir Tue Nov 14 14:42:19 2017
@@ -29,8 +29,7 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[TRUNC1]]
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[SUB]](s32)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC2]](s8)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB]](s32)
; CHECK: %x0 = COPY [[ANYEXT]](s64)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir Tue Nov 14 14:42:19 2017
@@ -13,4 +13,6 @@ body: |
; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[DEF]](s64), [[DEF1]](s64)
%0:_(s128) = G_IMPLICIT_DEF
+ %1:_(s64) = G_TRUNC %0
+ %x0 = COPY %1
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir Tue Nov 14 14:42:19 2017
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
@@ -10,30 +11,28 @@
name: test_vaarg
body: |
bb.0:
+ ; CHECK-LABEL: name: test_vaarg
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY %x0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8)
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[LOAD]], [[C]](s64)
+ ; CHECK: G_STORE [[GEP]](p0), [[COPY]](p0) :: (store 8)
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8)
+ ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[LOAD1]], [[C1]](s64)
+ ; CHECK: G_STORE [[GEP1]](p0), [[COPY]](p0) :: (store 8)
+ ; CHECK: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[COPY]](p0) :: (load 8)
+ ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
+ ; CHECK: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[LOAD2]], [[C2]](s64)
+ ; CHECK: [[PTR_MASK:%[0-9]+]]:_(p0) = G_PTR_MASK [[GEP2]], 4
+ ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; CHECK: [[GEP3:%[0-9]+]]:_(p0) = G_GEP [[PTR_MASK]], [[C3]](s64)
+ ; CHECK: G_STORE [[GEP3]](p0), [[COPY]](p0) :: (store 8)
%0:_(p0) = COPY %x0
- ; CHECK-LABEL: name: test_vaarg
- ; CHECK: [[LIST:%[0-9]+]]:_(p0) = G_LOAD %0(p0) :: (load 8)
- ; CHECK: %1:_(s8) = G_LOAD [[LIST]](p0) :: (load 1, align 8)
- ; CHECK: [[SLOTSIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK: [[NEXT:%[0-9]+]]:_(p0) = G_GEP [[LIST]], [[SLOTSIZE]](s64)
- ; CHECK: G_STORE [[NEXT]](p0), %0(p0) :: (store 8)
%1:_(s8) = G_VAARG %0(p0), 1
- ; CHECK: [[LIST:%[0-9]+]]:_(p0) = G_LOAD %0(p0) :: (load 8)
- ; CHECK: %2:_(s64) = G_LOAD [[LIST]](p0) :: (load 8)
- ; CHECK: [[SLOTSIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK: [[NEXT:%[0-9]+]]:_(p0) = G_GEP [[LIST]], [[SLOTSIZE]](s64)
- ; CHECK: G_STORE [[NEXT]](p0), %0(p0) :: (store 8)
%2:_(s64) = G_VAARG %0(p0), 8
- ; CHECK: [[LIST:%[0-9]+]]:_(p0) = G_LOAD %0(p0) :: (load 8)
- ; CHECK: [[ALIGNM1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
- ; CHECK: [[ALIGNTMP:%[0-9]+]]:_(p0) = G_GEP [[LIST]], [[ALIGNM1]](s64)
- ; CHECK: [[LIST:%[0-9]+]]:_(p0) = G_PTR_MASK [[ALIGNTMP]], 4
- ; CHECK: %3:_(s64) = G_LOAD [[LIST]](p0) :: (load 8, align 16)
- ; CHECK: [[SLOTSIZE:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; CHECK: [[NEXT:%[0-9]+]]:_(p0) = G_GEP [[LIST]], [[SLOTSIZE]](s64)
- ; CHECK: G_STORE [[NEXT]](p0), %0(p0) :: (store 8)
%3:_(s64) = G_VAARG %0(p0), 16
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir Tue Nov 14 14:42:19 2017
@@ -29,8 +29,7 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[TRUNC]], [[TRUNC1]]
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[XOR]](s32)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC2]](s8)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[XOR]](s32)
; CHECK: %x0 = COPY [[ANYEXT]](s64)
%0(s64) = COPY %x0
%1(s64) = COPY %x1
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir Tue Nov 14 14:42:19 2017
@@ -22,4 +22,5 @@ body: |
%0(s32) = COPY %vgpr0
%1(s32) = COPY %vgpr1
%2(s32) = G_ADD %0, %1
+ %vgpr0 = COPY %2
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir Tue Nov 14 14:42:19 2017
@@ -22,4 +22,5 @@ body: |
%0(s32) = COPY %vgpr0
%1(s32) = COPY %vgpr1
%2(s32) = G_AND %0, %1
+ %vgpr0 = COPY %2
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir Tue Nov 14 14:42:19 2017
@@ -22,4 +22,5 @@ body: |
%0(s32) = COPY %vgpr0
%1(<2 x s16>) = G_BITCAST %0
%2(s32) = G_BITCAST %1
+ %vgpr0 = COPY %2
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-constant.mir Tue Nov 14 14:42:19 2017
@@ -47,5 +47,7 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 7.500000e+00
%0(s32) = G_FCONSTANT float 1.0
+ %vgpr0 = COPY %0
%1(s32) = G_FCONSTANT float 7.5
+ %vgpr0 = COPY %1
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir Tue Nov 14 14:42:19 2017
@@ -23,4 +23,5 @@ body: |
%0(s32) = COPY %vgpr0
%1(s32) = COPY %vgpr1
%2(s32) = G_FADD %0, %1
+ %vgpr0 = COPY %2
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir Tue Nov 14 14:42:19 2017
@@ -22,4 +22,5 @@ body: |
%0(s32) = COPY %vgpr0
%1(s32) = COPY %vgpr1
%2(s32) = G_FMUL %0, %1
+ %vgpr0 = COPY %2
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir Tue Nov 14 14:42:19 2017
@@ -21,7 +21,11 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %vgpr0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[C]](s32), [[COPY]]
+ ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C]], [[COPY]]
+ ; CHECK: %vgpr0 = COPY [[SELECT]](s32)
%0(s32) = G_CONSTANT i32 0
%1(s32) = COPY %vgpr0
%2(s1) = G_ICMP intpred(ne), %0, %1
+ %3:_(s32) = G_SELECT %2(s1), %0(s32), %1(s32)
+ %vgpr0 = COPY %3
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir Tue Nov 14 14:42:19 2017
@@ -21,4 +21,5 @@ body: |
%0(s32) = COPY %vgpr0
%1(s32) = COPY %vgpr1
%2(s32) = G_OR %0, %1
+ %vgpr0 = COPY %2
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir Tue Nov 14 14:42:19 2017
@@ -31,5 +31,6 @@ body: |
%3(s32) = G_CONSTANT i32 1
%4(s32) = G_CONSTANT i32 2
%5(s32) = G_SELECT %2, %3, %4
+ %vgpr0 = COPY %5
...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir Tue Nov 14 14:42:19 2017
@@ -18,4 +18,5 @@ body: |
%0(s32) = COPY %vgpr0
%1(s32) = COPY %vgpr1
%2(s32) = G_SHL %0, %1
+ %vgpr0 = COPY %2
...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel.ll Tue Nov 14 14:42:19 2017
@@ -25,8 +25,9 @@ entry:
define signext i1 @test_sext_i1(i1 %x) {
; CHECK-LABEL: test_sext_i1
-; CHECK: and r0, r0, #1
-; CHECK: rsb r0, r0, #0
+; CHECK: mov r1, #31
+; CHECK: lsl r0, r0, r1
+; CHECK: asr r0, r0, r1
; CHECK: bx lr
entry:
ret i1 %x
@@ -34,15 +35,18 @@ entry:
define zeroext i8 @test_ext_i8(i8 %x) {
; CHECK-LABEL: test_ext_i8:
-; CHECK: uxtb r0, r0
+; CHECK: and r0, r0, #255
; CHECK: bx lr
+
entry:
ret i8 %x
}
define signext i16 @test_ext_i16(i16 %x) {
; CHECK-LABEL: test_ext_i16:
-; CHECK: sxth r0, r0
+; CHECK: mov r1, #16
+; CHECK: lsl r0, r0, r1
+; CHECK: asr r0, r0, r1
; CHECK: bx lr
entry:
ret i16 %x
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir Tue Nov 14 14:42:19 2017
@@ -139,8 +139,7 @@ body: |
; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SDIV
- ; CHECK: [[R16:%[0-9]+]]:_(s16) = G_TRUNC [[R32]]
- ; CHECK: [[R:%[0-9]+]]:_(s32) = G_SEXT [[R16]]
+ ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SDIV
%4(s16) = G_SDIV %1, %3
; CHECK: %r0 = COPY [[R]]
@@ -192,8 +191,7 @@ body: |
; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UDIV
- ; CHECK: [[R16:%[0-9]+]]:_(s16) = G_TRUNC [[R32]]
- ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ZEXT [[R16]]
+ ; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UDIV
%4(s16) = G_UDIV %1, %3
; CHECK: %r0 = COPY [[R]]
@@ -247,8 +245,7 @@ body: |
; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SDIV
- ; CHECK: [[R8:%[0-9]+]]:_(s8) = G_TRUNC [[R32]]
- ; CHECK: [[R:%[0-9]+]]:_(s32) = G_SEXT [[R8]]
+ ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SDIV
%4(s8) = G_SDIV %1, %3
; CHECK: %r0 = COPY [[R]]
@@ -300,8 +297,7 @@ body: |
; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UDIV
- ; CHECK: [[R8:%[0-9]+]]:_(s8) = G_TRUNC [[R32]]
- ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ZEXT [[R8]]
+ ; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UDIV
%4(s8) = G_UDIV %1, %3
; CHECK: %r0 = COPY [[R]]
@@ -433,8 +429,7 @@ body: |
; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SREM
- ; CHECK: [[R16:%[0-9]+]]:_(s16) = G_TRUNC [[R32]]
- ; CHECK: [[R:%[0-9]+]]:_(s32) = G_SEXT [[R16]]
+ ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SREM
%4(s16) = G_SREM %1, %3
; CHECK: %r0 = COPY [[R]]
@@ -488,8 +483,7 @@ body: |
; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UREM
- ; CHECK: [[R16:%[0-9]+]]:_(s16) = G_TRUNC [[R32]]
- ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ZEXT [[R16]]
+ ; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UREM
%4(s16) = G_UREM %1, %3
; CHECK: %r0 = COPY [[R]]
@@ -545,8 +539,7 @@ body: |
; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_SREM
- ; CHECK: [[R8:%[0-9]+]]:_(s8) = G_TRUNC [[R32]]
- ; CHECK: [[R:%[0-9]+]]:_(s32) = G_SEXT [[R8]]
+ ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ASHR
; SOFT-NOT: G_SREM
%4(s8) = G_SREM %1, %3
; CHECK: %r0 = COPY [[R]]
@@ -600,8 +593,7 @@ body: |
; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
; SOFT-NOT: G_UREM
- ; CHECK: [[R8:%[0-9]+]]:_(s8) = G_TRUNC [[R32]]
- ; CHECK: [[R:%[0-9]+]]:_(s32) = G_ZEXT [[R8]]
+ ; CHECK: [[R:%[0-9]+]]:_(s32) = G_AND
; SOFT-NOT: G_UREM
%4(s8) = G_UREM %1, %3
; CHECK: %r0 = COPY [[R]]
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir Tue Nov 14 14:42:19 2017
@@ -435,19 +435,23 @@ body: |
%0(s32) = COPY %r0
%1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
%2(s1) = G_FCMP floatpred(true), %0(s32), %1
+ %3(s32) = G_ZEXT %2(s1)
+ %r0 = COPY %3(s32)
+ BX_RET 14, _, implicit %r0
+ ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32)
+ ; For soft float we just need to return a '-1' constant, but the truncation
+ ; to 1 bit is converted by the combiner to the following masking sequence.
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]](s32)
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
- %3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_false_s32
@@ -468,19 +472,23 @@ body: |
%0(s32) = COPY %r0
%1(s32) = COPY %r1
- ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
- ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
%2(s1) = G_FCMP floatpred(false), %0(s32), %1
+ %3(s32) = G_ZEXT %2(s1)
+ %r0 = COPY %3(s32)
+ BX_RET 14, _, implicit %r0
+ ; HARD-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32)
+ ; For soft float we just need to return a '0' constant, but the truncation
+ ; to 1 bit is converted by the combiner to the following masking sequence.
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]](s32)
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
- %3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
- %r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]]
- BX_RET 14, _, implicit %r0
...
---
name: test_fcmp_oeq_s32
@@ -505,6 +513,7 @@ body: |
; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
%2(s1) = G_FCMP floatpred(oeq), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[X]](s32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: %r0 = COPY [[X]]
@@ -513,12 +522,16 @@ body: |
; SOFT-DEFAULT: BL $__eqsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+ ; For aeabi, we just need to truncate the result. The combiner changes the
+ ; truncation into the following masking sequence.
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0
@@ -546,6 +559,7 @@ body: |
; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
%2(s1) = G_FCMP floatpred(ogt), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[X]](s32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: %r0 = COPY [[X]]
@@ -554,12 +568,16 @@ body: |
; SOFT-DEFAULT: BL $__gtsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+ ; For aeabi, we just need to truncate the result. The combiner changes the
+ ; truncation into the following masking sequence.
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0
@@ -587,6 +605,7 @@ body: |
; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
%2(s1) = G_FCMP floatpred(oge), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[X]](s32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: %r0 = COPY [[X]]
@@ -595,12 +614,16 @@ body: |
; SOFT-DEFAULT: BL $__gesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+ ; For aeabi, we just need to truncate the result. The combiner changes the
+ ; truncation into the following masking sequence.
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0
@@ -628,6 +651,7 @@ body: |
; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
%2(s1) = G_FCMP floatpred(olt), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[X]](s32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: %r0 = COPY [[X]]
@@ -636,12 +660,16 @@ body: |
; SOFT-DEFAULT: BL $__ltsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+ ; For aeabi, we just need to truncate the result. The combiner changes the
+ ; truncation into the following masking sequence.
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0
@@ -669,6 +697,7 @@ body: |
; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
%2(s1) = G_FCMP floatpred(ole), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ole), [[X]](s32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: %r0 = COPY [[X]]
@@ -677,12 +706,16 @@ body: |
; SOFT-DEFAULT: BL $__lesf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+ ; For aeabi, we just need to truncate the result. The combiner changes the
+ ; truncation into the following masking sequence.
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0
@@ -955,6 +988,7 @@ body: |
; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
%2(s1) = G_FCMP floatpred(uno), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uno), [[X]](s32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: %r0 = COPY [[X]]
@@ -963,12 +997,16 @@ body: |
; SOFT-DEFAULT: BL $__unordsf2, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+ ; For aeabi, we just need to truncate the result. The combiner changes the
+ ; truncation into the following masking sequence.
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
+ ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0
@@ -996,6 +1034,7 @@ body: |
; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
%2(s1) = G_FCMP floatpred(one), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[X]](s32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: %r0 = COPY [[X]]
@@ -1020,11 +1059,14 @@ body: |
; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
- ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]]
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
+ ; The result of the G_OR needs to be truncated, and the combiner turns the
+ ; truncation into the following masking sequence.
+ ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]]
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0
@@ -1052,6 +1094,7 @@ body: |
; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
%2(s1) = G_FCMP floatpred(ueq), %0(s32), %1
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ueq), [[X]](s32), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: %r0 = COPY [[X]]
@@ -1076,11 +1119,14 @@ body: |
; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
- ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]]
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
+ ; The result of the G_OR needs to be truncated, and the combiner turns the
+ ; truncation into the following masking sequence.
+ ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]]
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
%3(s32) = G_ZEXT %2(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %3(s32)
; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0
@@ -1120,12 +1166,16 @@ body: |
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
%6(s1) = G_FCMP floatpred(true), %4(s64), %5
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(true), [[X]](s64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
- ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32)
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; The result needs to be truncated, and the combiner turns the truncation
+ ; into the following masking sequence.
+ ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]]
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0
@@ -1165,12 +1215,17 @@ body: |
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
%6(s1) = G_FCMP floatpred(false), %4(s64), %5
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(false), [[X]](s64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
+ ; SOFT-NOT: G_FCMP
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; The result needs to be truncated, and the combiner turns the truncation
+ ; into the following masking sequence.
+ ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]]
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]](s32)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0
@@ -1210,6 +1265,7 @@ body: |
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
%6(s1) = G_FCMP floatpred(oeq), %4(s64), %5
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[X]](s64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1220,12 +1276,16 @@ body: |
; SOFT-DEFAULT: BL $__eqdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+ ; For aeabi, we just need to truncate the result. The combiner changes the
+ ; truncation into the following masking sequence.
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[RET]](s32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0
@@ -1265,6 +1325,7 @@ body: |
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
%6(s1) = G_FCMP floatpred(ogt), %4(s64), %5
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[X]](s64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1275,12 +1336,16 @@ body: |
; SOFT-DEFAULT: BL $__gtdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+ ; For aeabi, we just need to truncate the result. The combiner changes the
+ ; truncation into the following masking sequence.
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[RET]](s32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0
@@ -1320,6 +1385,7 @@ body: |
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
%6(s1) = G_FCMP floatpred(oge), %4(s64), %5
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[X]](s64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1330,12 +1396,16 @@ body: |
; SOFT-DEFAULT: BL $__gedf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+ ; For aeabi, we just need to truncate the result. The combiner changes the
+ ; truncation into the following masking sequence.
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sge), [[RET]](s32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0
@@ -1375,6 +1445,7 @@ body: |
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
%6(s1) = G_FCMP floatpred(olt), %4(s64), %5
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(olt), [[X]](s64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1385,12 +1456,16 @@ body: |
; SOFT-DEFAULT: BL $__ltdf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+ ; For aeabi, we just need to truncate the result. The combiner changes the
+ ; truncation into the following masking sequence.
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[RET]](s32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0
@@ -1430,6 +1505,7 @@ body: |
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
%6(s1) = G_FCMP floatpred(ole), %4(s64), %5
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ole), [[X]](s64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1440,12 +1516,16 @@ body: |
; SOFT-DEFAULT: BL $__ledf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+ ; For aeabi, we just need to truncate the result. The combiner changes the
+ ; truncation into the following masking sequence.
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[RET]](s32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0
@@ -1814,6 +1894,7 @@ body: |
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
%6(s1) = G_FCMP floatpred(uno), %4(s64), %5
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(uno), [[X]](s64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1824,12 +1905,16 @@ body: |
; SOFT-DEFAULT: BL $__unorddf2, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0
; SOFT: [[RET:%[0-9]+]]:_(s32) = COPY %r0
; SOFT: ADJCALLSTACKUP
- ; SOFT-AEABI: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[RET]](s32)
+ ; For aeabi, we just need to truncate the result. The combiner changes the
+ ; truncation into the following masking sequence.
+ ; SOFT-AEABI: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT-AEABI: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[RET]](s32)
+ ; SOFT-AEABI: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-DEFAULT: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[RET]](s32), [[ZERO]]
+ ; SOFT-DEFAULT: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0
@@ -1869,6 +1954,7 @@ body: |
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
%6(s1) = G_FCMP floatpred(one), %4(s64), %5
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[X]](s64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1897,11 +1983,14 @@ body: |
; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
- ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]]
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
+ ; The result of the G_OR needs to be truncated, and the combiner turns the
+ ; truncation into the following masking sequence.
+ ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]]
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0
@@ -1941,6 +2030,7 @@ body: |
; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32)
%6(s1) = G_FCMP floatpred(ueq), %4(s64), %5
; HARD: [[R:%[0-9]+]]:_(s1) = G_FCMP floatpred(ueq), [[X]](s64), [[Y]]
+ ; HARD: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
; SOFT-NOT: G_FCMP
; SOFT: ADJCALLSTACKDOWN
; SOFT-DAG: %r0 = COPY [[X0]]
@@ -1969,11 +2059,14 @@ body: |
; SOFT-AEABI: [[R2EXT:%[0-9]+]]:_(s32) = COPY [[RET2]]
; SOFT-DEFAULT: [[R1EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R1]]
; SOFT-DEFAULT: [[R2EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[R2]]
- ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
- ; SOFT: [[R:%[0-9]+]]:_(s1) = G_TRUNC [[REXT]]
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = G_OR [[R1EXT]], [[R2EXT]]
+ ; The result of the G_OR needs to be truncated, and the combiner turns the
+ ; truncation into the following masking sequence.
+ ; SOFT: [[MASK:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; SOFT: [[RCOPY:%[0-9]+]]:_(s32) = COPY [[R]]
+ ; SOFT: [[REXT:%[0-9]+]]:_(s32) = G_AND [[RCOPY]], [[MASK]]
; SOFT-NOT: G_FCMP
%7(s32) = G_ZEXT %6(s1)
- ; CHECK: [[REXT:%[0-9]+]]:_(s32) = G_ZEXT [[R]](s1)
%r0 = COPY %7(s32)
; CHECK: %r0 = COPY [[REXT]]
BX_RET 14, _, implicit %r0
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/add-scalar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/add-scalar.ll?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/add-scalar.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/add-scalar.ll Tue Nov 14 14:42:19 2017
@@ -35,8 +35,8 @@ define i32 @test_add_i32(i32 %arg1, i32
;
; X32-LABEL: test_add_i32:
; X32: # BB#0:
-; X32-NEXT: movl 8(%esp), %eax
-; X32-NEXT: addl 4(%esp), %eax
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: addl {{[0-9]+}}(%esp), %eax
; X32-NEXT: retl
%ret = add i32 %arg1, %arg2
ret i32 %ret
@@ -53,8 +53,8 @@ define i16 @test_add_i16(i16 %arg1, i16
;
; X32-LABEL: test_add_i16:
; X32: # BB#0:
-; X32-NEXT: movzwl 8(%esp), %eax
-; X32-NEXT: addw 4(%esp), %ax
+; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: addw {{[0-9]+}}(%esp), %ax
; X32-NEXT: retl
%ret = add i16 %arg1, %arg2
ret i16 %ret
@@ -69,8 +69,8 @@ define i8 @test_add_i8(i8 %arg1, i8 %arg
;
; X32-LABEL: test_add_i8:
; X32: # BB#0:
-; X32-NEXT: movb 8(%esp), %al
-; X32-NEXT: addb 4(%esp), %al
+; X32-NEXT: movb {{[0-9]+}}(%esp), %al
+; X32-NEXT: addb {{[0-9]+}}(%esp), %al
; X32-NEXT: retl
%ret = add i8 %arg1, %arg2
ret i8 %ret
@@ -82,15 +82,17 @@ define i32 @test_add_i1(i32 %arg1, i32 %
; X64-NEXT: cmpl %esi, %edi
; X64-NEXT: sete %al
; X64-NEXT: addb %al, %al
+; X64-NEXT: movzbl %al, %eax
; X64-NEXT: andl $1, %eax
; X64-NEXT: retq
;
; X32-LABEL: test_add_i1:
; X32: # BB#0:
-; X32-NEXT: movl 8(%esp), %eax
-; X32-NEXT: cmpl %eax, 4(%esp)
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X32-NEXT: cmpl %eax, {{[0-9]+}}(%esp)
; X32-NEXT: sete %al
; X32-NEXT: addb %al, %al
+; X32-NEXT: movzbl %al, %eax
; X32-NEXT: andl $1, %eax
; X32-NEXT: retl
%c = icmp eq i32 %arg1, %arg2
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/and-scalar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/and-scalar.ll?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/and-scalar.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/and-scalar.ll Tue Nov 14 14:42:19 2017
@@ -7,6 +7,7 @@ define i32 @test_and_i1(i32 %arg1, i32 %
; ALL-NEXT: cmpl %esi, %edi
; ALL-NEXT: sete %al
; ALL-NEXT: andb %al, %al
+; ALL-NEXT: movzbl %al, %eax
; ALL-NEXT: andl $1, %eax
; ALL-NEXT: retq
%c = icmp eq i32 %arg1, %arg2
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/ext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/ext.ll?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/ext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/ext.ll Tue Nov 14 14:42:19 2017
@@ -11,7 +11,7 @@ define i8 @test_zext_i1toi8(i32 %a) {
;
; X32-LABEL: test_zext_i1toi8:
; X32: # BB#0:
-; X32-NEXT: movl 4(%esp), %eax
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: andb $1, %al
; X32-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill>
; X32-NEXT: retl
@@ -29,7 +29,7 @@ define i16 @test_zext_i1toi16(i32 %a) {
;
; X32-LABEL: test_zext_i1toi16:
; X32: # BB#0:
-; X32-NEXT: movl 4(%esp), %eax
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: andw $1, %ax
; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
; X32-NEXT: retl
@@ -47,7 +47,7 @@ define i32 @test_zext_i1(i32 %a) {
;
; X32-LABEL: test_zext_i1:
; X32: # BB#0:
-; X32-NEXT: movl 4(%esp), %eax
+; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: andl $1, %eax
; X32-NEXT: retl
%val = trunc i32 %a to i1
@@ -63,7 +63,7 @@ define i32 @test_zext_i8(i8 %val) {
;
; X32-LABEL: test_zext_i8:
; X32: # BB#0:
-; X32-NEXT: movzbl 4(%esp), %eax
+; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: retl
%r = zext i8 %val to i32
ret i32 %r
@@ -77,7 +77,7 @@ define i32 @test_zext_i16(i16 %val) {
;
; X32-LABEL: test_zext_i16:
; X32: # BB#0:
-; X32-NEXT: movzwl 4(%esp), %eax
+; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-NEXT: retl
%r = zext i16 %val to i32
ret i32 %r
@@ -91,7 +91,7 @@ define i32 @test_sext_i8(i8 %val) {
;
; X32-LABEL: test_sext_i8:
; X32: # BB#0:
-; X32-NEXT: movsbl 4(%esp), %eax
+; X32-NEXT: movsbl {{[0-9]+}}(%esp), %eax
; X32-NEXT: retl
%r = sext i8 %val to i32
ret i32 %r
@@ -105,7 +105,7 @@ define i32 @test_sext_i16(i16 %val) {
;
; X32-LABEL: test_sext_i16:
; X32: # BB#0:
-; X32-NEXT: movswl 4(%esp), %eax
+; X32-NEXT: movswl {{[0-9]+}}(%esp), %eax
; X32-NEXT: retl
%r = sext i16 %val to i32
ret i32 %r
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add-v128.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add-v128.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add-v128.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add-v128.mir Tue Nov 14 14:42:19 2017
@@ -39,10 +39,12 @@ body: |
; ALL: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
; ALL: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
; ALL: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[DEF]], [[DEF1]]
+ ; ALL: %xmm0 = COPY [[ADD]](<16 x s8>)
; ALL: RET 0
%0(<16 x s8>) = IMPLICIT_DEF
%1(<16 x s8>) = IMPLICIT_DEF
%2(<16 x s8>) = G_ADD %0, %1
+ %xmm0 = COPY %2
RET 0
...
@@ -63,10 +65,12 @@ body: |
; ALL: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
; ALL: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
; ALL: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[DEF1]]
+ ; ALL: %xmm0 = COPY [[ADD]](<8 x s16>)
; ALL: RET 0
%0(<8 x s16>) = IMPLICIT_DEF
%1(<8 x s16>) = IMPLICIT_DEF
%2(<8 x s16>) = G_ADD %0, %1
+ %xmm0 = COPY %2
RET 0
...
@@ -87,10 +91,12 @@ body: |
; ALL: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
; ALL: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
; ALL: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[DEF1]]
+ ; ALL: %xmm0 = COPY [[ADD]](<4 x s32>)
; ALL: RET 0
%0(<4 x s32>) = IMPLICIT_DEF
%1(<4 x s32>) = IMPLICIT_DEF
%2(<4 x s32>) = G_ADD %0, %1
+ %xmm0 = COPY %2
RET 0
...
@@ -111,10 +117,12 @@ body: |
; ALL: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
; ALL: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
; ALL: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[DEF]], [[DEF1]]
+ ; ALL: %xmm0 = COPY [[ADD]](<2 x s64>)
; ALL: RET 0
%0(<2 x s64>) = IMPLICIT_DEF
%1(<2 x s64>) = IMPLICIT_DEF
%2(<2 x s64>) = G_ADD %0, %1
+ %xmm0 = COPY %2
RET 0
...
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir Tue Nov 14 14:42:19 2017
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NOT_AVX2 --check-prefix=SSE2
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NOT_AVX2 --check-prefix=AVX1
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX2
@@ -26,7 +27,6 @@
...
---
name: test_add_v32i8
-# ALL-LABEL: name: test_add_v32i8
alignment: 4
legalized: false
regBankSelected: false
@@ -34,32 +34,37 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# NOT_AVX2: %0:_(<32 x s8>) = IMPLICIT_DEF
-# NOT_AVX2-NEXT: %1:_(<32 x s8>) = IMPLICIT_DEF
-# NOT_AVX2-NEXT: %3:_(<16 x s8>), %4:_(<16 x s8>) = G_UNMERGE_VALUES %0(<32 x s8>)
-# NOT_AVX2-NEXT: %5:_(<16 x s8>), %6:_(<16 x s8>) = G_UNMERGE_VALUES %1(<32 x s8>)
-# NOT_AVX2-NEXT: %7:_(<16 x s8>) = G_ADD %3, %5
-# NOT_AVX2-NEXT: %8:_(<16 x s8>) = G_ADD %4, %6
-# NOT_AVX2-NEXT: %2:_(<32 x s8>) = G_MERGE_VALUES %7(<16 x s8>), %8(<16 x s8>)
-# NOT_AVX2-NEXT: RET 0
-#
-# AVX2: %0:_(<32 x s8>) = IMPLICIT_DEF
-# AVX2-NEXT: %1:_(<32 x s8>) = IMPLICIT_DEF
-# AVX2-NEXT: %2:_(<32 x s8>) = G_ADD %0, %1
-# AVX2-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %ymm0, %ymm1
+ ; CHECK-LABEL: name: test_add_v32i8
+ ; ALL: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
+ ; SSE2: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<32 x s8>)
+ ; SSE2: [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF1]](<32 x s8>)
+ ; AVX1: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<32 x s8>)
+ ; AVX1: [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF1]](<32 x s8>)
+ ; SSE2: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV]], [[UV2]]
+ ; SSE2: [[ADD1:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV1]], [[UV3]]
+ ; AVX1: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV]], [[UV2]]
+ ; AVX1: [[ADD1:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV1]], [[UV3]]
+ ; SSE2: [[MV:%[0-9]+]]:_(<32 x s8>) = G_MERGE_VALUES [[ADD]](<16 x s8>), [[ADD1]](<16 x s8>)
+ ; AVX1: [[MV:%[0-9]+]]:_(<32 x s8>) = G_MERGE_VALUES [[ADD]](<16 x s8>), [[ADD1]](<16 x s8>)
+ ; SSE2: %ymm0 = COPY [[MV]](<32 x s8>)
+ ; AVX1: %ymm0 = COPY [[MV]](<32 x s8>)
+ ; AVX2: [[ADD:%[0-9]+]]:_(<32 x s8>) = G_ADD [[DEF]], [[DEF1]]
+ ; AVX2: %ymm0 = COPY [[ADD]](<32 x s8>)
+ ; ALL: RET 0
%0(<32 x s8>) = IMPLICIT_DEF
%1(<32 x s8>) = IMPLICIT_DEF
%2(<32 x s8>) = G_ADD %0, %1
+ %ymm0 = COPY %2
RET 0
...
---
name: test_add_v16i16
-# ALL-LABEL: name: test_add_v16i16
alignment: 4
legalized: false
regBankSelected: false
@@ -67,32 +72,37 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# NOT_AVX2: %0:_(<16 x s16>) = IMPLICIT_DEF
-# NOT_AVX2-NEXT: %1:_(<16 x s16>) = IMPLICIT_DEF
-# NOT_AVX2-NEXT: %3:_(<8 x s16>), %4:_(<8 x s16>) = G_UNMERGE_VALUES %0(<16 x s16>)
-# NOT_AVX2-NEXT: %5:_(<8 x s16>), %6:_(<8 x s16>) = G_UNMERGE_VALUES %1(<16 x s16>)
-# NOT_AVX2-NEXT: %7:_(<8 x s16>) = G_ADD %3, %5
-# NOT_AVX2-NEXT: %8:_(<8 x s16>) = G_ADD %4, %6
-# NOT_AVX2-NEXT: %2:_(<16 x s16>) = G_MERGE_VALUES %7(<8 x s16>), %8(<8 x s16>)
-# NOT_AVX2-NEXT: RET 0
-#
-# AVX2: %0:_(<16 x s16>) = IMPLICIT_DEF
-# AVX2-NEXT: %1:_(<16 x s16>) = IMPLICIT_DEF
-# AVX2-NEXT: %2:_(<16 x s16>) = G_ADD %0, %1
-# AVX2-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %ymm0, %ymm1
+ ; ALL-LABEL: name: test_add_v16i16
+ ; ALL: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
+ ; SSE2: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<16 x s16>)
+ ; SSE2: [[UV2:%[0-9]+]]:_(<8 x s16>), [[UV3:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF1]](<16 x s16>)
+ ; SSE2: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV]], [[UV2]]
+ ; SSE2: [[ADD1:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV1]], [[UV3]]
+ ; SSE2: [[MV:%[0-9]+]]:_(<16 x s16>) = G_MERGE_VALUES [[ADD]](<8 x s16>), [[ADD1]](<8 x s16>)
+ ; AVX1: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<16 x s16>)
+ ; AVX1: [[UV2:%[0-9]+]]:_(<8 x s16>), [[UV3:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF1]](<16 x s16>)
+ ; AVX1: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV]], [[UV2]]
+ ; AVX1: [[ADD1:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV1]], [[UV3]]
+ ; AVX1: [[MV:%[0-9]+]]:_(<16 x s16>) = G_MERGE_VALUES [[ADD]](<8 x s16>), [[ADD1]](<8 x s16>)
+ ; SSE2: %ymm0 = COPY [[MV]](<16 x s16>)
+ ; AVX1: %ymm0 = COPY [[MV]](<16 x s16>)
+ ; AVX2: [[ADD:%[0-9]+]]:_(<16 x s16>) = G_ADD [[DEF]], [[DEF1]]
+ ; AVX2: %ymm0 = COPY [[ADD]](<16 x s16>)
+ ; ALL: RET 0
%0(<16 x s16>) = IMPLICIT_DEF
%1(<16 x s16>) = IMPLICIT_DEF
%2(<16 x s16>) = G_ADD %0, %1
+ %ymm0 = COPY %2
RET 0
...
---
name: test_add_v8i32
-# ALL-LABEL: name: test_add_v8i32
alignment: 4
legalized: false
regBankSelected: false
@@ -100,32 +110,37 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# NOT_AVX2: %0:_(<8 x s32>) = IMPLICIT_DEF
-# NOT_AVX2-NEXT: %1:_(<8 x s32>) = IMPLICIT_DEF
-# NOT_AVX2-NEXT: %3:_(<4 x s32>), %4:_(<4 x s32>) = G_UNMERGE_VALUES %0(<8 x s32>)
-# NOT_AVX2-NEXT: %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %1(<8 x s32>)
-# NOT_AVX2-NEXT: %7:_(<4 x s32>) = G_ADD %3, %5
-# NOT_AVX2-NEXT: %8:_(<4 x s32>) = G_ADD %4, %6
-# NOT_AVX2-NEXT: %2:_(<8 x s32>) = G_MERGE_VALUES %7(<4 x s32>), %8(<4 x s32>)
-# NOT_AVX2-NEXT: RET 0
-#
-# AVX2: %0:_(<8 x s32>) = IMPLICIT_DEF
-# AVX2-NEXT: %1:_(<8 x s32>) = IMPLICIT_DEF
-# AVX2-NEXT: %2:_(<8 x s32>) = G_ADD %0, %1
-# AVX2-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %ymm0, %ymm1
+ ; ALL-LABEL: name: test_add_v8i32
+ ; ALL: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
+ ; SSE2: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<8 x s32>)
+ ; SSE2: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF1]](<8 x s32>)
+ ; SSE2: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV]], [[UV2]]
+ ; SSE2: [[ADD1:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV1]], [[UV3]]
+ ; SSE2: [[MV:%[0-9]+]]:_(<8 x s32>) = G_MERGE_VALUES [[ADD]](<4 x s32>), [[ADD1]](<4 x s32>)
+ ; SSE2: %ymm0 = COPY [[MV]](<8 x s32>)
+ ; AVX1: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<8 x s32>)
+ ; AVX1: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF1]](<8 x s32>)
+ ; AVX1: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV]], [[UV2]]
+ ; AVX1: [[ADD1:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV1]], [[UV3]]
+ ; AVX1: [[MV:%[0-9]+]]:_(<8 x s32>) = G_MERGE_VALUES [[ADD]](<4 x s32>), [[ADD1]](<4 x s32>)
+ ; AVX1: %ymm0 = COPY [[MV]](<8 x s32>)
+ ; AVX2: [[ADD:%[0-9]+]]:_(<8 x s32>) = G_ADD [[DEF]], [[DEF1]]
+ ; AVX2: %ymm0 = COPY [[ADD]](<8 x s32>)
+ ; ALL: RET 0
%0(<8 x s32>) = IMPLICIT_DEF
%1(<8 x s32>) = IMPLICIT_DEF
%2(<8 x s32>) = G_ADD %0, %1
+ %ymm0 = COPY %2
RET 0
...
---
name: test_add_v4i64
-# ALL-LABEL: name: test_add_v4i64
alignment: 4
legalized: false
regBankSelected: false
@@ -133,26 +148,32 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# NOT_AVX2: %0:_(<4 x s64>) = IMPLICIT_DEF
-# NOT_AVX2-NEXT: %1:_(<4 x s64>) = IMPLICIT_DEF
-# NOT_AVX2-NEXT: %3:_(<2 x s64>), %4:_(<2 x s64>) = G_UNMERGE_VALUES %0(<4 x s64>)
-# NOT_AVX2-NEXT: %5:_(<2 x s64>), %6:_(<2 x s64>) = G_UNMERGE_VALUES %1(<4 x s64>)
-# NOT_AVX2-NEXT: %7:_(<2 x s64>) = G_ADD %3, %5
-# NOT_AVX2-NEXT: %8:_(<2 x s64>) = G_ADD %4, %6
-# NOT_AVX2-NEXT: %2:_(<4 x s64>) = G_MERGE_VALUES %7(<2 x s64>), %8(<2 x s64>)
-# NOT_AVX2-NEXT: RET 0
-#
-# AVX2: %0:_(<4 x s64>) = IMPLICIT_DEF
-# AVX2-NEXT: %1:_(<4 x s64>) = IMPLICIT_DEF
-# AVX2-NEXT: %2:_(<4 x s64>) = G_ADD %0, %1
-# AVX2-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %ymm0, %ymm1
+ ; ALL-LABEL: name: test_add_v4i64
+ ; ALL: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
+ ; SSE2: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
+ ; SSE2: [[UV2:%[0-9]+]]:_(<2 x s64>), [[UV3:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF1]](<4 x s64>)
+ ; SSE2: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV]], [[UV2]]
+ ; SSE2: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV1]], [[UV3]]
+ ; SSE2: [[MV:%[0-9]+]]:_(<4 x s64>) = G_MERGE_VALUES [[ADD]](<2 x s64>), [[ADD1]](<2 x s64>)
+ ; AVX1: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
+ ; AVX1: [[UV2:%[0-9]+]]:_(<2 x s64>), [[UV3:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF1]](<4 x s64>)
+ ; AVX1: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV]], [[UV2]]
+ ; AVX1: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV1]], [[UV3]]
+ ; AVX1: [[MV:%[0-9]+]]:_(<4 x s64>) = G_MERGE_VALUES [[ADD]](<2 x s64>), [[ADD1]](<2 x s64>)
+ ; SSE2: %ymm0 = COPY [[MV]](<4 x s64>)
+ ; AVX1: %ymm0 = COPY [[MV]](<4 x s64>)
+ ; AVX2: [[ADD:%[0-9]+]]:_(<4 x s64>) = G_ADD [[DEF]], [[DEF1]]
+ ; AVX2: %ymm0 = COPY [[ADD]](<4 x s64>)
+ ; ALL: RET 0
%0(<4 x s64>) = IMPLICIT_DEF
%1(<4 x s64>) = IMPLICIT_DEF
%2(<4 x s64>) = G_ADD %0, %1
+ %ymm0 = COPY %2
RET 0
...
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir Tue Nov 14 14:42:19 2017
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX1
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512F
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512bw -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512BW
@@ -30,7 +31,6 @@
...
---
name: test_add_v64i8
-# ALL-LABEL: name: test_add_v64i8
alignment: 4
legalized: false
regBankSelected: false
@@ -38,43 +38,39 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# AVX1: %0:_(<64 x s8>) = IMPLICIT_DEF
-# AVX1-NEXT: %1:_(<64 x s8>) = IMPLICIT_DEF
-# AVX1-NEXT: %3:_(<16 x s8>), %4:_(<16 x s8>), %5:_(<16 x s8>), %6:_(<16 x s8>) = G_UNMERGE_VALUES %0(<64 x s8>)
-# AVX1-NEXT: %7:_(<16 x s8>), %8:_(<16 x s8>), %9:_(<16 x s8>), %10:_(<16 x s8>) = G_UNMERGE_VALUES %1(<64 x s8>)
-# AVX1-NEXT: %11:_(<16 x s8>) = G_ADD %3, %7
-# AVX1-NEXT: %12:_(<16 x s8>) = G_ADD %4, %8
-# AVX1-NEXT: %13:_(<16 x s8>) = G_ADD %5, %9
-# AVX1-NEXT: %14:_(<16 x s8>) = G_ADD %6, %10
-# AVX1-NEXT: %2:_(<64 x s8>) = G_MERGE_VALUES %11(<16 x s8>), %12(<16 x s8>), %13(<16 x s8>), %14(<16 x s8>)
-# AVX1-NEXT: RET 0
-#
-# AVX512F: %0:_(<64 x s8>) = IMPLICIT_DEF
-# AVX512F-NEXT: %1:_(<64 x s8>) = IMPLICIT_DEF
-# AVX512F-NEXT: %3:_(<32 x s8>), %4:_(<32 x s8>) = G_UNMERGE_VALUES %0(<64 x s8>)
-# AVX512F-NEXT: %5:_(<32 x s8>), %6:_(<32 x s8>) = G_UNMERGE_VALUES %1(<64 x s8>)
-# AVX512F-NEXT: %7:_(<32 x s8>) = G_ADD %3, %5
-# AVX512F-NEXT: %8:_(<32 x s8>) = G_ADD %4, %6
-# AVX512F-NEXT: %2:_(<64 x s8>) = G_MERGE_VALUES %7(<32 x s8>), %8(<32 x s8>)
-# AVX512F-NEXT: RET 0
-#
-# AVX512BW: %0:_(<64 x s8>) = IMPLICIT_DEF
-# AVX512BW-NEXT: %1:_(<64 x s8>) = IMPLICIT_DEF
-# AVX512BW-NEXT: %2:_(<64 x s8>) = G_ADD %0, %1
-# AVX512BW-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %zmm0, %zmm1
+ ; ALL-LABEL: name: test_add_v64i8
+ ; ALL: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
+ ; AVX1: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>), [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<64 x s8>)
+ ; AVX1: [[UV4:%[0-9]+]]:_(<16 x s8>), [[UV5:%[0-9]+]]:_(<16 x s8>), [[UV6:%[0-9]+]]:_(<16 x s8>), [[UV7:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF1]](<64 x s8>)
+ ; AVX1: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV]], [[UV4]]
+ ; AVX1: [[ADD1:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV1]], [[UV5]]
+ ; AVX1: [[ADD2:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV2]], [[UV6]]
+ ; AVX1: [[ADD3:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV3]], [[UV7]]
+ ; AVX1: [[MV:%[0-9]+]]:_(<64 x s8>) = G_MERGE_VALUES [[ADD]](<16 x s8>), [[ADD1]](<16 x s8>), [[ADD2]](<16 x s8>), [[ADD3]](<16 x s8>)
+ ; AVX1: %zmm0 = COPY [[MV]](<64 x s8>)
+ ; AVX512F: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF]](<64 x s8>)
+ ; AVX512F: [[UV2:%[0-9]+]]:_(<32 x s8>), [[UV3:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF1]](<64 x s8>)
+ ; AVX512F: [[ADD:%[0-9]+]]:_(<32 x s8>) = G_ADD [[UV]], [[UV2]]
+ ; AVX512F: [[ADD1:%[0-9]+]]:_(<32 x s8>) = G_ADD [[UV1]], [[UV3]]
+ ; AVX512F: [[MV:%[0-9]+]]:_(<64 x s8>) = G_MERGE_VALUES [[ADD]](<32 x s8>), [[ADD1]](<32 x s8>)
+ ; AVX512F: %zmm0 = COPY [[MV]](<64 x s8>)
+ ; AVX512BW: [[ADD:%[0-9]+]]:_(<64 x s8>) = G_ADD [[DEF]], [[DEF1]]
+ ; AVX512BW: %zmm0 = COPY [[ADD]](<64 x s8>)
+ ; ALL: RET 0
%0(<64 x s8>) = IMPLICIT_DEF
%1(<64 x s8>) = IMPLICIT_DEF
%2(<64 x s8>) = G_ADD %0, %1
+ %zmm0 = COPY %2
RET 0
...
---
name: test_add_v32i16
-# ALL-LABEL: name: test_add_v32i16
alignment: 4
legalized: false
regBankSelected: false
@@ -82,43 +78,39 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# AVX1: %0:_(<32 x s16>) = IMPLICIT_DEF
-# AVX1-NEXT: %1:_(<32 x s16>) = IMPLICIT_DEF
-# AVX1-NEXT: %3:_(<8 x s16>), %4:_(<8 x s16>), %5:_(<8 x s16>), %6:_(<8 x s16>) = G_UNMERGE_VALUES %0(<32 x s16>)
-# AVX1-NEXT: %7:_(<8 x s16>), %8:_(<8 x s16>), %9:_(<8 x s16>), %10:_(<8 x s16>) = G_UNMERGE_VALUES %1(<32 x s16>)
-# AVX1-NEXT: %11:_(<8 x s16>) = G_ADD %3, %7
-# AVX1-NEXT: %12:_(<8 x s16>) = G_ADD %4, %8
-# AVX1-NEXT: %13:_(<8 x s16>) = G_ADD %5, %9
-# AVX1-NEXT: %14:_(<8 x s16>) = G_ADD %6, %10
-# AVX1-NEXT: %2:_(<32 x s16>) = G_MERGE_VALUES %11(<8 x s16>), %12(<8 x s16>), %13(<8 x s16>), %14(<8 x s16>)
-# AVX1-NEXT: RET 0
-#
-# AVX512F: %0:_(<32 x s16>) = IMPLICIT_DEF
-# AVX512F-NEXT: %1:_(<32 x s16>) = IMPLICIT_DEF
-# AVX512F-NEXT: %3:_(<16 x s16>), %4:_(<16 x s16>) = G_UNMERGE_VALUES %0(<32 x s16>)
-# AVX512F-NEXT: %5:_(<16 x s16>), %6:_(<16 x s16>) = G_UNMERGE_VALUES %1(<32 x s16>)
-# AVX512F-NEXT: %7:_(<16 x s16>) = G_ADD %3, %5
-# AVX512F-NEXT: %8:_(<16 x s16>) = G_ADD %4, %6
-# AVX512F-NEXT: %2:_(<32 x s16>) = G_MERGE_VALUES %7(<16 x s16>), %8(<16 x s16>)
-# AVX512F-NEXT: RET 0
-#
-# AVX512BW: %0:_(<32 x s16>) = IMPLICIT_DEF
-# AVX512BW-NEXT: %1:_(<32 x s16>) = IMPLICIT_DEF
-# AVX512BW-NEXT: %2:_(<32 x s16>) = G_ADD %0, %1
-# AVX512BW-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %zmm0, %zmm1
+ ; ALL-LABEL: name: test_add_v32i16
+ ; ALL: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
+ ; AVX1: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>), [[UV2:%[0-9]+]]:_(<8 x s16>), [[UV3:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<32 x s16>)
+ ; AVX1: [[UV4:%[0-9]+]]:_(<8 x s16>), [[UV5:%[0-9]+]]:_(<8 x s16>), [[UV6:%[0-9]+]]:_(<8 x s16>), [[UV7:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF1]](<32 x s16>)
+ ; AVX1: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV]], [[UV4]]
+ ; AVX1: [[ADD1:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV1]], [[UV5]]
+ ; AVX1: [[ADD2:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV2]], [[UV6]]
+ ; AVX1: [[ADD3:%[0-9]+]]:_(<8 x s16>) = G_ADD [[UV3]], [[UV7]]
+ ; AVX1: [[MV:%[0-9]+]]:_(<32 x s16>) = G_MERGE_VALUES [[ADD]](<8 x s16>), [[ADD1]](<8 x s16>), [[ADD2]](<8 x s16>), [[ADD3]](<8 x s16>)
+ ; AVX1: %zmm0 = COPY [[MV]](<32 x s16>)
+ ; AVX512F: [[UV:%[0-9]+]]:_(<16 x s16>), [[UV1:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF]](<32 x s16>)
+ ; AVX512F: [[UV2:%[0-9]+]]:_(<16 x s16>), [[UV3:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF1]](<32 x s16>)
+ ; AVX512F: [[ADD:%[0-9]+]]:_(<16 x s16>) = G_ADD [[UV]], [[UV2]]
+ ; AVX512F: [[ADD1:%[0-9]+]]:_(<16 x s16>) = G_ADD [[UV1]], [[UV3]]
+ ; AVX512F: [[MV:%[0-9]+]]:_(<32 x s16>) = G_MERGE_VALUES [[ADD]](<16 x s16>), [[ADD1]](<16 x s16>)
+ ; AVX512F: %zmm0 = COPY [[MV]](<32 x s16>)
+ ; AVX512BW: [[ADD:%[0-9]+]]:_(<32 x s16>) = G_ADD [[DEF]], [[DEF1]]
+ ; AVX512BW: %zmm0 = COPY [[ADD]](<32 x s16>)
+ ; ALL: RET 0
%0(<32 x s16>) = IMPLICIT_DEF
%1(<32 x s16>) = IMPLICIT_DEF
%2(<32 x s16>) = G_ADD %0, %1
+ %zmm0 = COPY %2
RET 0
...
---
name: test_add_v16i32
-# ALL-LABEL: name: test_add_v16i32
alignment: 4
legalized: false
regBankSelected: false
@@ -126,39 +118,35 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# AVX1: %0:_(<16 x s32>) = IMPLICIT_DEF
-# AVX1-NEXT: %1:_(<16 x s32>) = IMPLICIT_DEF
-# AVX1-NEXT: %3:_(<4 x s32>), %4:_(<4 x s32>), %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %0(<16 x s32>)
-# AVX1-NEXT: %7:_(<4 x s32>), %8:_(<4 x s32>), %9:_(<4 x s32>), %10:_(<4 x s32>) = G_UNMERGE_VALUES %1(<16 x s32>)
-# AVX1-NEXT: %11:_(<4 x s32>) = G_ADD %3, %7
-# AVX1-NEXT: %12:_(<4 x s32>) = G_ADD %4, %8
-# AVX1-NEXT: %13:_(<4 x s32>) = G_ADD %5, %9
-# AVX1-NEXT: %14:_(<4 x s32>) = G_ADD %6, %10
-# AVX1-NEXT: %2:_(<16 x s32>) = G_MERGE_VALUES %11(<4 x s32>), %12(<4 x s32>), %13(<4 x s32>), %14(<4 x s32>)
-# AVX1-NEXT: RET 0
-#
-# AVX512F: %0:_(<16 x s32>) = IMPLICIT_DEF
-# AVX512F-NEXT: %1:_(<16 x s32>) = IMPLICIT_DEF
-# AVX512F-NEXT: %2:_(<16 x s32>) = G_ADD %0, %1
-# AVX512F-NEXT: RET 0
-#
-# AVX512BW: %0:_(<16 x s32>) = IMPLICIT_DEF
-# AVX512BW-NEXT: %1:_(<16 x s32>) = IMPLICIT_DEF
-# AVX512BW-NEXT: %2:_(<16 x s32>) = G_ADD %0, %1
-# AVX512BW-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %zmm0, %zmm1
+ ; ALL-LABEL: name: test_add_v16i32
+ ; ALL: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
+ ; AVX1: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>), [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)
+ ; AVX1: [[UV4:%[0-9]+]]:_(<4 x s32>), [[UV5:%[0-9]+]]:_(<4 x s32>), [[UV6:%[0-9]+]]:_(<4 x s32>), [[UV7:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF1]](<16 x s32>)
+ ; AVX1: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV]], [[UV4]]
+ ; AVX1: [[ADD1:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV1]], [[UV5]]
+ ; AVX1: [[ADD2:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV2]], [[UV6]]
+ ; AVX1: [[ADD3:%[0-9]+]]:_(<4 x s32>) = G_ADD [[UV3]], [[UV7]]
+ ; AVX1: [[MV:%[0-9]+]]:_(<16 x s32>) = G_MERGE_VALUES [[ADD]](<4 x s32>), [[ADD1]](<4 x s32>), [[ADD2]](<4 x s32>), [[ADD3]](<4 x s32>)
+ ; AVX1: %zmm0 = COPY [[MV]](<16 x s32>)
+ ; AVX512F: [[ADD:%[0-9]+]]:_(<16 x s32>) = G_ADD [[DEF]], [[DEF1]]
+ ; AVX512F: %zmm0 = COPY [[ADD]](<16 x s32>)
+ ; AVX512BW: [[ADD:%[0-9]+]]:_(<16 x s32>) = G_ADD [[DEF]], [[DEF1]]
+ ; AVX512BW: %zmm0 = COPY [[ADD]](<16 x s32>)
+ ; ALL: RET 0
%0(<16 x s32>) = IMPLICIT_DEF
%1(<16 x s32>) = IMPLICIT_DEF
%2(<16 x s32>) = G_ADD %0, %1
+ %zmm0 = COPY %2
RET 0
...
---
name: test_add_v8i64
-# ALL-LABEL: name: test_add_v8i64
alignment: 4
legalized: false
regBankSelected: false
@@ -166,39 +154,35 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# AVX1: %0:_(<8 x s64>) = IMPLICIT_DEF
-# AVX1-NEXT: %1:_(<8 x s64>) = IMPLICIT_DEF
-# AVX1-NEXT: %3:_(<2 x s64>), %4:_(<2 x s64>), %5:_(<2 x s64>), %6:_(<2 x s64>) = G_UNMERGE_VALUES %0(<8 x s64>)
-# AVX1-NEXT: %7:_(<2 x s64>), %8:_(<2 x s64>), %9:_(<2 x s64>), %10:_(<2 x s64>) = G_UNMERGE_VALUES %1(<8 x s64>)
-# AVX1-NEXT: %11:_(<2 x s64>) = G_ADD %3, %7
-# AVX1-NEXT: %12:_(<2 x s64>) = G_ADD %4, %8
-# AVX1-NEXT: %13:_(<2 x s64>) = G_ADD %5, %9
-# AVX1-NEXT: %14:_(<2 x s64>) = G_ADD %6, %10
-# AVX1-NEXT: %2:_(<8 x s64>) = G_MERGE_VALUES %11(<2 x s64>), %12(<2 x s64>), %13(<2 x s64>), %14(<2 x s64>)
-# AVX1-NEXT: RET 0
-#
-# AVX512F: %0:_(<8 x s64>) = IMPLICIT_DEF
-# AVX512F-NEXT: %1:_(<8 x s64>) = IMPLICIT_DEF
-# AVX512F-NEXT: %2:_(<8 x s64>) = G_ADD %0, %1
-# AVX512F-NEXT: RET 0
-#
-# AVX512BW: %0:_(<8 x s64>) = IMPLICIT_DEF
-# AVX512BW-NEXT: %1:_(<8 x s64>) = IMPLICIT_DEF
-# AVX512BW-NEXT: %2:_(<8 x s64>) = G_ADD %0, %1
-# AVX512BW-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
liveins: %zmm0, %zmm1
+ ; ALL-LABEL: name: test_add_v8i64
+ ; ALL: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
+ ; ALL: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
+ ; AVX1: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>), [[UV2:%[0-9]+]]:_(<2 x s64>), [[UV3:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF]](<8 x s64>)
+ ; AVX1: [[UV4:%[0-9]+]]:_(<2 x s64>), [[UV5:%[0-9]+]]:_(<2 x s64>), [[UV6:%[0-9]+]]:_(<2 x s64>), [[UV7:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF1]](<8 x s64>)
+ ; AVX1: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV]], [[UV4]]
+ ; AVX1: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV1]], [[UV5]]
+ ; AVX1: [[ADD2:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV2]], [[UV6]]
+ ; AVX1: [[ADD3:%[0-9]+]]:_(<2 x s64>) = G_ADD [[UV3]], [[UV7]]
+ ; AVX1: [[MV:%[0-9]+]]:_(<8 x s64>) = G_MERGE_VALUES [[ADD]](<2 x s64>), [[ADD1]](<2 x s64>), [[ADD2]](<2 x s64>), [[ADD3]](<2 x s64>)
+ ; AVX1: %zmm0 = COPY [[MV]](<8 x s64>)
+ ; AVX512F: [[ADD:%[0-9]+]]:_(<8 x s64>) = G_ADD [[DEF]], [[DEF1]]
+ ; AVX512F: %zmm0 = COPY [[ADD]](<8 x s64>)
+ ; AVX512BW: [[ADD:%[0-9]+]]:_(<8 x s64>) = G_ADD [[DEF]], [[DEF1]]
+ ; AVX512BW: %zmm0 = COPY [[ADD]](<8 x s64>)
+ ; ALL: RET 0
%0(<8 x s64>) = IMPLICIT_DEF
%1(<8 x s64>) = IMPLICIT_DEF
%2(<8 x s64>) = G_ADD %0, %1
+ %zmm0 = COPY %2
RET 0
...
---
name: test_add_v64i8_2
-# ALL-LABEL: name: test_add_v64i8_2
alignment: 4
legalized: false
regBankSelected: false
@@ -212,49 +196,40 @@ registers:
- { id: 6, class: _ }
- { id: 7, class: _ }
- { id: 8, class: _ }
-# AVX1: %2:_(<32 x s8>) = COPY %ymm0
-# AVX1-NEXT: %3:_(<32 x s8>) = COPY %ymm1
-# AVX1-NEXT: %4:_(<32 x s8>) = COPY %ymm2
-# AVX1-NEXT: %5:_(<32 x s8>) = COPY %ymm3
-# AVX1-NEXT: %9:_(<16 x s8>), %10:_(<16 x s8>) = G_UNMERGE_VALUES %2(<32 x s8>)
-# AVX1-NEXT: %11:_(<16 x s8>), %12:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
-# AVX1-NEXT: %13:_(<16 x s8>), %14:_(<16 x s8>) = G_UNMERGE_VALUES %4(<32 x s8>)
-# AVX1-NEXT: %15:_(<16 x s8>), %16:_(<16 x s8>) = G_UNMERGE_VALUES %5(<32 x s8>)
-# AVX1-NEXT: %17:_(<16 x s8>) = G_ADD %9, %13
-# AVX1-NEXT: %18:_(<16 x s8>) = G_ADD %10, %14
-# AVX1-NEXT: %19:_(<16 x s8>) = G_ADD %11, %15
-# AVX1-NEXT: %20:_(<16 x s8>) = G_ADD %12, %16
-# AVX1-NEXT: %7:_(<32 x s8>) = G_MERGE_VALUES %17(<16 x s8>), %18(<16 x s8>)
-# AVX1-NEXT: %8:_(<32 x s8>) = G_MERGE_VALUES %19(<16 x s8>), %20(<16 x s8>)
-# AVX1-NEXT: %ymm0 = COPY %7(<32 x s8>)
-# AVX1-NEXT: %ymm1 = COPY %8(<32 x s8>)
-# AVX1-NEXT: RET 0, implicit %ymm0, implicit %ymm1
#
-# AVX512F: %2:_(<32 x s8>) = COPY %ymm0
-# AVX512F-NEXT: %3:_(<32 x s8>) = COPY %ymm1
-# AVX512F-NEXT: %4:_(<32 x s8>) = COPY %ymm2
-# AVX512F-NEXT: %5:_(<32 x s8>) = COPY %ymm3
-# AVX512F-NEXT: %13:_(<32 x s8>) = G_ADD %2, %4
-# AVX512F-NEXT: %14:_(<32 x s8>) = G_ADD %3, %5
-# AVX512F-NEXT: %ymm0 = COPY %13(<32 x s8>)
-# AVX512F-NEXT: %ymm1 = COPY %14(<32 x s8>)
-# AVX512F-NEXT: RET 0, implicit %ymm0, implicit %ymm1
#
-# AVX512BW: %2:_(<32 x s8>) = COPY %ymm0
-# AVX512BW-NEXT: %3:_(<32 x s8>) = COPY %ymm1
-# AVX512BW-NEXT: %4:_(<32 x s8>) = COPY %ymm2
-# AVX512BW-NEXT: %5:_(<32 x s8>) = COPY %ymm3
-# AVX512BW-NEXT: %0:_(<64 x s8>) = G_MERGE_VALUES %2(<32 x s8>), %3(<32 x s8>)
-# AVX512BW-NEXT: %1:_(<64 x s8>) = G_MERGE_VALUES %4(<32 x s8>), %5(<32 x s8>)
-# AVX512BW-NEXT: %6:_(<64 x s8>) = G_ADD %0, %1
-# AVX512BW-NEXT: %7:_(<32 x s8>), %8:_(<32 x s8>) = G_UNMERGE_VALUES %6(<64 x s8>)
-# AVX512BW-NEXT: %ymm0 = COPY %7(<32 x s8>)
-# AVX512BW-NEXT: %ymm1 = COPY %8(<32 x s8>)
-# AVX512BW-NEXT: RET 0, implicit %ymm0, implicit %ymm1
body: |
bb.1 (%ir-block.0):
liveins: %ymm0, %ymm1, %ymm2, %ymm3
+ ; ALL-LABEL: name: test_add_v64i8_2
+ ; ALL: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY %ymm0
+ ; ALL: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY %ymm1
+ ; ALL: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY %ymm2
+ ; ALL: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY %ymm3
+ ; AVX1: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[COPY]](<32 x s8>)
+ ; AVX1: [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[COPY1]](<32 x s8>)
+ ; AVX1: [[UV4:%[0-9]+]]:_(<16 x s8>), [[UV5:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[COPY2]](<32 x s8>)
+ ; AVX1: [[UV6:%[0-9]+]]:_(<16 x s8>), [[UV7:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[COPY3]](<32 x s8>)
+ ; AVX1: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV]], [[UV4]]
+ ; AVX1: [[ADD1:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV1]], [[UV5]]
+ ; AVX1: [[ADD2:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV2]], [[UV6]]
+ ; AVX1: [[ADD3:%[0-9]+]]:_(<16 x s8>) = G_ADD [[UV3]], [[UV7]]
+ ; AVX1: [[MV:%[0-9]+]]:_(<32 x s8>) = G_MERGE_VALUES [[ADD]](<16 x s8>), [[ADD1]](<16 x s8>)
+ ; AVX1: [[MV1:%[0-9]+]]:_(<32 x s8>) = G_MERGE_VALUES [[ADD2]](<16 x s8>), [[ADD3]](<16 x s8>)
+ ; AVX1: %ymm0 = COPY [[MV]](<32 x s8>)
+ ; AVX1: %ymm1 = COPY [[MV1]](<32 x s8>)
+ ; AVX512F: [[ADD:%[0-9]+]]:_(<32 x s8>) = G_ADD [[COPY]], [[COPY2]]
+ ; AVX512F: [[ADD1:%[0-9]+]]:_(<32 x s8>) = G_ADD [[COPY1]], [[COPY3]]
+ ; AVX512F: %ymm0 = COPY [[ADD]](<32 x s8>)
+ ; AVX512F: %ymm1 = COPY [[ADD1]](<32 x s8>)
+ ; AVX512BW: [[MV:%[0-9]+]]:_(<64 x s8>) = G_MERGE_VALUES [[COPY]](<32 x s8>), [[COPY1]](<32 x s8>)
+ ; AVX512BW: [[MV1:%[0-9]+]]:_(<64 x s8>) = G_MERGE_VALUES [[COPY2]](<32 x s8>), [[COPY3]](<32 x s8>)
+ ; AVX512BW: [[ADD:%[0-9]+]]:_(<64 x s8>) = G_ADD [[MV]], [[MV1]]
+ ; AVX512BW: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[ADD]](<64 x s8>)
+ ; AVX512BW: %ymm0 = COPY [[UV]](<32 x s8>)
+ ; AVX512BW: %ymm1 = COPY [[UV1]](<32 x s8>)
+ ; ALL: RET 0, implicit %ymm0, implicit %ymm1
%2(<32 x s8>) = COPY %ymm0
%3(<32 x s8>) = COPY %ymm1
%4(<32 x s8>) = COPY %ymm2
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-add.mir Tue Nov 14 14:42:19 2017
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
--- |
@@ -21,19 +22,35 @@ registers:
# CHECK-NEXT: %3(s8) = G_TRUNC %0(s32)
# CHECK-NEXT: %4(s8) = G_TRUNC %0(s32)
# CHECK-NEXT: %5(s8) = G_ADD %3, %4
-# CHECK-NEXT: %2(s1) = G_TRUNC %5(s8)
-# CHECK-NEXT: RET 0
+# CHECK: RET 0
body: |
bb.1 (%ir-block.0):
+ ; X64-LABEL: name: test_add_i1
+ ; X64: [[COPY:%[0-9]+]]:_(s32) = COPY %edx
+ ; X64: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; X64: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; X64: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]]
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s8)
+ ; X64: %eax = COPY [[ANYEXT]](s32)
+ ; X64: RET 0
+ ; X32-LABEL: name: test_add_i1
+ ; X32: [[COPY:%[0-9]+]]:_(s32) = COPY %edx
+ ; X32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; X32: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; X32: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]]
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ADD]](s8)
+ ; X32: %eax = COPY [[ANYEXT]](s32)
+ ; X32: RET 0
%0(s32) = COPY %edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_ADD %1, %1
+ %3:_(s32) = G_ANYEXT %2
+ %eax = COPY %3
RET 0
...
---
name: test_add_i32
-# ALL-LABEL: name: test_add_i32
alignment: 4
legalized: false
regBankSelected: false
@@ -41,21 +58,29 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# ALL: %0:_(s32) = IMPLICIT_DEF
-# ALL-NEXT: %1:_(s32) = IMPLICIT_DEF
-# ALL-NEXT: %2:_(s32) = G_ADD %0, %1
-# ALL-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
+ ; X64-LABEL: name: test_add_i32
+ ; X64: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
+ ; X64: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
+ ; X64: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[DEF]], [[DEF1]]
+ ; X64: %eax = COPY [[ADD]](s32)
+ ; X64: RET 0
+ ; X32-LABEL: name: test_add_i32
+ ; X32: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
+ ; X32: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
+ ; X32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[DEF]], [[DEF1]]
+ ; X32: %eax = COPY [[ADD]](s32)
+ ; X32: RET 0
%0(s32) = IMPLICIT_DEF
%1(s32) = IMPLICIT_DEF
%2(s32) = G_ADD %0, %1
+ %eax = COPY %2
RET 0
...
---
name: test_add_i64
-# ALL-LABEL: name: test_add_i64
alignment: 4
legalized: false
regBankSelected: false
@@ -63,26 +88,30 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# X64: %0:_(s64) = IMPLICIT_DEF
-# X64-NEXT: %1:_(s64) = IMPLICIT_DEF
-# X64-NEXT: %2:_(s64) = G_ADD %0, %1
-# X64-NEXT: RET 0
-#
-# X32: %0:_(s64) = IMPLICIT_DEF
-# X32-NEXT: %1:_(s64) = IMPLICIT_DEF
-# X32-NEXT: %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %0(s64)
-# X32-NEXT: %5:_(s32), %6:_(s32) = G_UNMERGE_VALUES %1(s64)
-# X32-NEXT: %12:_(s8) = G_CONSTANT i8 0
-# X32-NEXT: %7:_(s1) = G_TRUNC %12(s8)
-# X32-NEXT: %8:_(s32), %9:_(s1) = G_UADDE %3, %5, %7
-# X32-NEXT: %10:_(s32), %11:_(s1) = G_UADDE %4, %6, %9
-# X32-NEXT: %2:_(s64) = G_MERGE_VALUES %8(s32), %10(s32)
-# X32-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
+ ; X64-LABEL: name: test_add_i64
+ ; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X64: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X64: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[DEF]], [[DEF1]]
+ ; X64: %rax = COPY [[ADD]](s64)
+ ; X64: RET 0
+ ; X32-LABEL: name: test_add_i64
+ ; X32: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X32: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
+ ; X32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
+ ; X32: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
+ ; X32: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0
+ ; X32: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s8)
+ ; X32: [[UADDE:%[0-9]+]]:_(s32), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[UV]], [[UV2]], [[TRUNC]]
+ ; X32: [[UADDE2:%[0-9]+]]:_(s32), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[UV1]], [[UV3]], [[UADDE1]]
+ ; X32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UADDE]](s32), [[UADDE2]](s32)
+ ; X32: %rax = COPY [[MV]](s64)
+ ; X32: RET 0
%0(s64) = IMPLICIT_DEF
%1(s64) = IMPLICIT_DEF
%2(s64) = G_ADD %0, %1
+ %rax = COPY %2
RET 0
...
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir Tue Nov 14 14:42:19 2017
@@ -45,11 +45,14 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[TRUNC1]]
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[AND]](s8)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s8)
+ ; CHECK: %eax = COPY [[ANYEXT]](s32)
; CHECK: RET 0
%0(s32) = COPY %edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_AND %1, %1
+ %3:_(s32) = G_ANYEXT %2
+ %eax = COPY %3
RET 0
...
---
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-constant.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-constant.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-constant.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-constant.mir Tue Nov 14 14:42:19 2017
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=i386-linux-gnu -mattr=+sse2 -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
@@ -8,7 +9,6 @@
...
---
name: test_constant
-# ALL-LABEL: name: test_constant
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -17,40 +17,73 @@ registers:
- { id: 4, class: _ }
body: |
bb.1 (%ir-block.0):
- ; ALL: %5:_(s8) = G_CONSTANT i8 -1
- ; ALL: %0:_(s1) = G_TRUNC %5(s8)
+ ; X32-LABEL: name: test_constant
+ ; X32: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s8)
+ ; X32: %eax = COPY [[ANYEXT]](s32)
+ ; X32: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 8
+ ; X32: %al = COPY [[C1]](s8)
+ ; X32: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 16
+ ; X32: %ax = COPY [[C2]](s16)
+ ; X32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; X32: %eax = COPY [[C3]](s32)
+ ; X32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+ ; X32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; X32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C4]](s32), [[C5]](s32)
+ ; X32: %rax = COPY [[MV]](s64)
+ ; X32: RET 0
+ ; X64-LABEL: name: test_constant
+ ; X64: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C]](s8)
+ ; X64: %eax = COPY [[ANYEXT]](s32)
+ ; X64: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 8
+ ; X64: %al = COPY [[C1]](s8)
+ ; X64: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 16
+ ; X64: %ax = COPY [[C2]](s16)
+ ; X64: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
+ ; X64: %eax = COPY [[C3]](s32)
+ ; X64: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 64
+ ; X64: %rax = COPY [[C4]](s64)
+ ; X64: RET 0
%0(s1) = G_CONSTANT i1 1
+ %5:_(s32) = G_ANYEXT %0
+ %eax = COPY %5
- ; ALL: %1:_(s8) = G_CONSTANT i8 8
%1(s8) = G_CONSTANT i8 8
-
- ; ALL: %2:_(s16) = G_CONSTANT i16 16
+ %al = COPY %1
%2(s16) = G_CONSTANT i16 16
+ %ax = COPY %2
- ; ALL: %3:_(s32) = G_CONSTANT i32 32
%3(s32) = G_CONSTANT i32 32
+ %eax = COPY %3
- ; X64: %4:_(s64) = G_CONSTANT i64 64
- ; X32: %6:_(s32) = G_CONSTANT i32 64
- ; X32: %7:_(s32) = G_CONSTANT i32 0
- ; X32: %4:_(s64) = G_MERGE_VALUES %6(s32), %7(s32)
%4(s64) = G_CONSTANT i64 64
+ %rax = COPY %4
RET 0
...
---
name: test_fconstant
-# ALL-LABEL: name: test_fconstant
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
- ; ALL: %0:_(s32) = G_FCONSTANT float 1.000000e+00
- ; ALL: %1:_(s64) = G_FCONSTANT double 2.000000e+00
+ ; X32-LABEL: name: test_fconstant
+ ; X32: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+ ; X32: %eax = COPY [[C]](s32)
+ ; X32: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
+ ; X32: %rax = COPY [[C1]](s64)
+ ; X64-LABEL: name: test_fconstant
+ ; X64: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
+ ; X64: %eax = COPY [[C]](s32)
+ ; X64: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
+ ; X64: %rax = COPY [[C1]](s64)
%0(s32) = G_FCONSTANT float 1.0
+ %eax = COPY %0
%1(s64) = G_FCONSTANT double 2.0
+ %rax = COPY %1
...
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir Tue Nov 14 14:42:19 2017
@@ -172,9 +172,10 @@ body: |
; CHECK-LABEL: name: test_zext_i1
; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s8)
- ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC]](s1)
- ; CHECK: %rax = COPY [[ZEXT]](s64)
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
+ ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C]]
+ ; CHECK: %rax = COPY [[AND]](s64)
; CHECK: RET 0, implicit %rax
%0(s8) = COPY %dil
%1(s1) = G_TRUNC %0(s8)
@@ -267,8 +268,7 @@ body: |
; CHECK-LABEL: name: test_anyext_i1
; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s8)
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[TRUNC]](s1)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s8)
; CHECK: %rax = COPY [[ANYEXT]](s64)
; CHECK: RET 0, implicit %rax
%0(s8) = COPY %dil
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-ext.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-ext.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-ext.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-ext.mir Tue Nov 14 14:42:19 2017
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
--- |
@@ -91,21 +92,26 @@
...
---
name: test_zext_i1toi8
-# ALL-LABEL: name: test_zext_i1toi8
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-# ALL: %0:_(s1) = COPY %edi
-# ALL-NEXT: %1:_(s8) = G_ZEXT %0(s1)
-# ALL-NEXT: %al = COPY %1(s8)
-# ALL-NEXT: RET 0, implicit %al
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; X32-LABEL: name: test_zext_i1toi8
+ ; X32: [[COPY:%[0-9]+]]:_(s1) = COPY %edi
+ ; X32: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[COPY]](s1)
+ ; X32: %al = COPY [[ZEXT]](s8)
+ ; X32: RET 0, implicit %al
+ ; X64-LABEL: name: test_zext_i1toi8
+ ; X64: [[COPY:%[0-9]+]]:_(s1) = COPY %edi
+ ; X64: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[COPY]](s1)
+ ; X64: %al = COPY [[ZEXT]](s8)
+ ; X64: RET 0, implicit %al
%0(s1) = COPY %edi
%1(s8) = G_ZEXT %0(s1)
%al = COPY %1(s8)
@@ -114,21 +120,26 @@ body: |
...
---
name: test_zext_i1toi16
-# ALL-LABEL: name: test_zext_i1toi16
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-# ALL: %0:_(s1) = COPY %edi
-# ALL-NEXT: %1:_(s16) = G_ZEXT %0(s1)
-# ALL-NEXT: %ax = COPY %1(s16)
-# ALL-NEXT: RET 0, implicit %ax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; X32-LABEL: name: test_zext_i1toi16
+ ; X32: [[COPY:%[0-9]+]]:_(s1) = COPY %edi
+ ; X32: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[COPY]](s1)
+ ; X32: %ax = COPY [[ZEXT]](s16)
+ ; X32: RET 0, implicit %ax
+ ; X64-LABEL: name: test_zext_i1toi16
+ ; X64: [[COPY:%[0-9]+]]:_(s1) = COPY %edi
+ ; X64: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[COPY]](s1)
+ ; X64: %ax = COPY [[ZEXT]](s16)
+ ; X64: RET 0, implicit %ax
%0(s1) = COPY %edi
%1(s16) = G_ZEXT %0(s1)
%ax = COPY %1(s16)
@@ -137,7 +148,6 @@ body: |
...
---
name: test_zext_i1
-# ALL-LABEL: name: test_zext_i1
alignment: 4
legalized: false
regBankSelected: false
@@ -145,15 +155,24 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# ALL: %0:_(s8) = COPY %dil
-# ALL-NEXT: %1:_(s1) = G_TRUNC %0(s8)
-# ALL-NEXT: %2:_(s32) = G_ZEXT %1(s1)
-# ALL-NEXT: %eax = COPY %2(s32)
-# ALL-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; X32-LABEL: name: test_zext_i1
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
+ ; X32: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+ ; X32: %eax = COPY [[AND]](s32)
+ ; X32: RET 0, implicit %eax
+ ; X64-LABEL: name: test_zext_i1
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
+ ; X64: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+ ; X64: %eax = COPY [[AND]](s32)
+ ; X64: RET 0, implicit %eax
%0(s8) = COPY %dil
%1(s1) = G_TRUNC %0(s8)
%2(s32) = G_ZEXT %1(s1)
@@ -163,21 +182,26 @@ body: |
...
---
name: test_zext_i8toi16
-# ALL-LABEL: name: test_zext_i8toi16
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-# ALL: %0:_(s8) = COPY %dil
-# ALL-NEXT: %1:_(s16) = G_ZEXT %0(s8)
-# ALL-NEXT: %ax = COPY %1(s16)
-# ALL-NEXT: RET 0, implicit %ax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; X32-LABEL: name: test_zext_i8toi16
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X32: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[COPY]](s8)
+ ; X32: %ax = COPY [[ZEXT]](s16)
+ ; X32: RET 0, implicit %ax
+ ; X64-LABEL: name: test_zext_i8toi16
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X64: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[COPY]](s8)
+ ; X64: %ax = COPY [[ZEXT]](s16)
+ ; X64: RET 0, implicit %ax
%0(s8) = COPY %dil
%1(s16) = G_ZEXT %0(s8)
%ax = COPY %1(s16)
@@ -186,21 +210,26 @@ body: |
...
---
name: test_zext_i8
-# ALL-LABEL: name: test_zext_i8
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# ALL: %0:_(s8) = COPY %dil
-# ALL-NEXT: %1:_(s32) = G_ZEXT %0(s8)
-# ALL-NEXT: %eax = COPY %1(s32)
-# ALL-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; X32-LABEL: name: test_zext_i8
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X32: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s8)
+ ; X32: %eax = COPY [[ZEXT]](s32)
+ ; X32: RET 0, implicit %eax
+ ; X64-LABEL: name: test_zext_i8
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X64: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s8)
+ ; X64: %eax = COPY [[ZEXT]](s32)
+ ; X64: RET 0, implicit %eax
%0(s8) = COPY %dil
%1(s32) = G_ZEXT %0(s8)
%eax = COPY %1(s32)
@@ -209,21 +238,26 @@ body: |
...
---
name: test_zext_i16
-# ALL-LABEL: name: test_zext_i16
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# ALL: %0:_(s16) = COPY %di
-# ALL-NEXT: %1:_(s32) = G_ZEXT %0(s16)
-# ALL-NEXT: %eax = COPY %1(s32)
-# ALL-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; X32-LABEL: name: test_zext_i16
+ ; X32: [[COPY:%[0-9]+]]:_(s16) = COPY %di
+ ; X32: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s16)
+ ; X32: %eax = COPY [[ZEXT]](s32)
+ ; X32: RET 0, implicit %eax
+ ; X64-LABEL: name: test_zext_i16
+ ; X64: [[COPY:%[0-9]+]]:_(s16) = COPY %di
+ ; X64: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[COPY]](s16)
+ ; X64: %eax = COPY [[ZEXT]](s32)
+ ; X64: RET 0, implicit %eax
%0(s16) = COPY %di
%1(s32) = G_ZEXT %0(s16)
%eax = COPY %1(s32)
@@ -232,22 +266,25 @@ body: |
...
---
name: test_sext_i1toi8
-# ALL-LABEL: name: test_sext_i1toi8
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-# ALL: %0:_(s1) = COPY %edi
-# ALL-NEXT: %1:_(s8) = G_SEXT %0(s1)
-# ALL-NEXT: %al = COPY %1(s8)
-# ALL-NEXT: RET 0, implicit %al
body: |
bb.1 (%ir-block.0):
liveins: %edi
- %0(s1) = COPY %edi
+ ; X32-LABEL: name: test_sext_i1toi8
+ ; X32: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
+ ; X32: %al = COPY [[DEF]](s8)
+ ; X32: RET 0, implicit %al
+ ; X64-LABEL: name: test_sext_i1toi8
+ ; X64: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
+ ; X64: %al = COPY [[DEF]](s8)
+ ; X64: RET 0, implicit %al
+ %0(s1) = G_IMPLICIT_DEF
%1(s8) = G_SEXT %0(s1)
%al = COPY %1(s8)
RET 0, implicit %al
@@ -255,22 +292,25 @@ body: |
...
---
name: test_sext_i1toi16
-# ALL-LABEL: name: test_sext_i1toi16
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-# ALL: %0:_(s1) = COPY %edi
-# ALL-NEXT: %1:_(s16) = G_SEXT %0(s1)
-# ALL-NEXT: %ax = COPY %1(s16)
-# ALL-NEXT: RET 0, implicit %ax
body: |
bb.1 (%ir-block.0):
liveins: %edi
- %0(s1) = COPY %edi
+ ; X32-LABEL: name: test_sext_i1toi16
+ ; X32: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; X32: %ax = COPY [[DEF]](s16)
+ ; X32: RET 0, implicit %ax
+ ; X64-LABEL: name: test_sext_i1toi16
+ ; X64: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; X64: %ax = COPY [[DEF]](s16)
+ ; X64: RET 0, implicit %ax
+ %0(s1) = G_IMPLICIT_DEF
%1(s16) = G_SEXT %0(s1)
%ax = COPY %1(s16)
RET 0, implicit %ax
@@ -278,7 +318,6 @@ body: |
...
---
name: test_sext_i1
-# ALL-LABEL: name: test_sext_i1
alignment: 4
legalized: false
regBankSelected: false
@@ -286,39 +325,46 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# ALL: %0:_(s8) = COPY %dil
-# ALL-NEXT: %1:_(s1) = G_TRUNC %0(s8)
-# ALL-NEXT: %2:_(s32) = G_SEXT %1(s1)
-# ALL-NEXT: %eax = COPY %2(s32)
-# ALL-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi
- %0(s8) = COPY %dil
- %1(s1) = G_TRUNC %0(s8)
- %2(s32) = G_SEXT %1(s1)
+ ; X32-LABEL: name: test_sext_i1
+ ; X32: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; X32: %eax = COPY [[DEF]](s32)
+ ; X32: RET 0, implicit %eax
+ ; X64-LABEL: name: test_sext_i1
+ ; X64: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; X64: %eax = COPY [[DEF]](s32)
+ ; X64: RET 0, implicit %eax
+ %0(s1) = G_IMPLICIT_DEF
+ %2(s32) = G_SEXT %0(s1)
%eax = COPY %2(s32)
RET 0, implicit %eax
...
---
name: test_sext_i8toi16
-# ALL-LABEL: name: test_sext_i8toi16
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-# ALL: %0:_(s8) = COPY %dil
-# ALL-NEXT: %1:_(s16) = G_SEXT %0(s8)
-# ALL-NEXT: %ax = COPY %1(s16)
-# ALL-NEXT: RET 0, implicit %ax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; X32-LABEL: name: test_sext_i8toi16
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X32: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[COPY]](s8)
+ ; X32: %ax = COPY [[SEXT]](s16)
+ ; X32: RET 0, implicit %ax
+ ; X64-LABEL: name: test_sext_i8toi16
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X64: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[COPY]](s8)
+ ; X64: %ax = COPY [[SEXT]](s16)
+ ; X64: RET 0, implicit %ax
%0(s8) = COPY %dil
%1(s16) = G_SEXT %0(s8)
%ax = COPY %1(s16)
@@ -327,21 +373,26 @@ body: |
...
---
name: test_sext_i8
-# ALL-LABEL: name: test_sext_i8
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# ALL: %0:_(s8) = COPY %dil
-# ALL-NEXT: %1:_(s32) = G_SEXT %0(s8)
-# ALL-NEXT: %eax = COPY %1(s32)
-# ALL-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; X32-LABEL: name: test_sext_i8
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X32: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s8)
+ ; X32: %eax = COPY [[SEXT]](s32)
+ ; X32: RET 0, implicit %eax
+ ; X64-LABEL: name: test_sext_i8
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X64: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s8)
+ ; X64: %eax = COPY [[SEXT]](s32)
+ ; X64: RET 0, implicit %eax
%0(s8) = COPY %dil
%1(s32) = G_SEXT %0(s8)
%eax = COPY %1(s32)
@@ -350,21 +401,26 @@ body: |
...
---
name: test_sext_i16
-# ALL-LABEL: name: test_sext_i16
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# ALL: %0:_(s16) = COPY %di
-# ALL-NEXT: %1:_(s32) = G_SEXT %0(s16)
-# ALL-NEXT: %eax = COPY %1(s32)
-# ALL-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; X32-LABEL: name: test_sext_i16
+ ; X32: [[COPY:%[0-9]+]]:_(s16) = COPY %di
+ ; X32: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s16)
+ ; X32: %eax = COPY [[SEXT]](s32)
+ ; X32: RET 0, implicit %eax
+ ; X64-LABEL: name: test_sext_i16
+ ; X64: [[COPY:%[0-9]+]]:_(s16) = COPY %di
+ ; X64: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s16)
+ ; X64: %eax = COPY [[SEXT]](s32)
+ ; X64: RET 0, implicit %eax
%0(s16) = COPY %di
%1(s32) = G_SEXT %0(s16)
%eax = COPY %1(s32)
@@ -373,21 +429,26 @@ body: |
...
---
name: test_anyext_i1toi8
-# ALL-LABEL: name: test_anyext_i1toi8
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-# ALL: %0:_(s1) = COPY %edi
-# ALL-NEXT: %1:_(s8) = G_ANYEXT %0(s1)
-# ALL-NEXT: %al = COPY %1(s8)
-# ALL-NEXT: RET 0, implicit %al
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; X32-LABEL: name: test_anyext_i1toi8
+ ; X32: [[COPY:%[0-9]+]]:_(s1) = COPY %edi
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s8) = G_ANYEXT [[COPY]](s1)
+ ; X32: %al = COPY [[ANYEXT]](s8)
+ ; X32: RET 0, implicit %al
+ ; X64-LABEL: name: test_anyext_i1toi8
+ ; X64: [[COPY:%[0-9]+]]:_(s1) = COPY %edi
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s8) = G_ANYEXT [[COPY]](s1)
+ ; X64: %al = COPY [[ANYEXT]](s8)
+ ; X64: RET 0, implicit %al
%0(s1) = COPY %edi
%1(s8) = G_ANYEXT %0(s1)
%al = COPY %1(s8)
@@ -396,21 +457,26 @@ body: |
...
---
name: test_anyext_i1toi16
-# ALL-LABEL: name: test_anyext_i1toi16
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-# ALL: %0:_(s1) = COPY %edi
-# ALL-NEXT: %1:_(s16) = G_ANYEXT %0(s1)
-# ALL-NEXT: %ax = COPY %1(s16)
-# ALL-NEXT: RET 0, implicit %ax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; X32-LABEL: name: test_anyext_i1toi16
+ ; X32: [[COPY:%[0-9]+]]:_(s1) = COPY %edi
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s1)
+ ; X32: %ax = COPY [[ANYEXT]](s16)
+ ; X32: RET 0, implicit %ax
+ ; X64-LABEL: name: test_anyext_i1toi16
+ ; X64: [[COPY:%[0-9]+]]:_(s1) = COPY %edi
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s1)
+ ; X64: %ax = COPY [[ANYEXT]](s16)
+ ; X64: RET 0, implicit %ax
%0(s1) = COPY %edi
%1(s16) = G_ANYEXT %0(s1)
%ax = COPY %1(s16)
@@ -419,7 +485,6 @@ body: |
...
---
name: test_anyext_i1
-# ALL-LABEL: name: test_anyext_i1
alignment: 4
legalized: false
regBankSelected: false
@@ -427,15 +492,20 @@ registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# ALL: %0:_(s8) = COPY %dil
-# ALL-NEXT: %1:_(s1) = G_TRUNC %0(s8)
-# ALL-NEXT: %2:_(s32) = G_ANYEXT %1(s1)
-# ALL-NEXT: %eax = COPY %2(s32)
-# ALL-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; X32-LABEL: name: test_anyext_i1
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
+ ; X32: %eax = COPY [[ANYEXT]](s32)
+ ; X32: RET 0, implicit %eax
+ ; X64-LABEL: name: test_anyext_i1
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
+ ; X64: %eax = COPY [[ANYEXT]](s32)
+ ; X64: RET 0, implicit %eax
%0(s8) = COPY %dil
%1(s1) = G_TRUNC %0(s8)
%2(s32) = G_ANYEXT %1(s1)
@@ -445,21 +515,26 @@ body: |
...
---
name: test_anyext_i8toi16
-# ALL-LABEL: name: test_anyext_i8toi16
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
-# ALL: %0:_(s8) = COPY %dil
-# ALL-NEXT: %1:_(s16) = G_ANYEXT %0(s8)
-# ALL-NEXT: %ax = COPY %1(s16)
-# ALL-NEXT: RET 0, implicit %ax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; X32-LABEL: name: test_anyext_i8toi16
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
+ ; X32: %ax = COPY [[ANYEXT]](s16)
+ ; X32: RET 0, implicit %ax
+ ; X64-LABEL: name: test_anyext_i8toi16
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
+ ; X64: %ax = COPY [[ANYEXT]](s16)
+ ; X64: RET 0, implicit %ax
%0(s8) = COPY %dil
%1(s16) = G_ANYEXT %0(s8)
%ax = COPY %1(s16)
@@ -468,21 +543,26 @@ body: |
...
---
name: test_anyext_i8
-# ALL-LABEL: name: test_anyext_i8
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# ALL: %0:_(s8) = COPY %dil
-# ALL-NEXT: %1:_(s32) = G_ANYEXT %0(s8)
-# ALL-NEXT: %eax = COPY %1(s32)
-# ALL-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; X32-LABEL: name: test_anyext_i8
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
+ ; X32: %eax = COPY [[ANYEXT]](s32)
+ ; X32: RET 0, implicit %eax
+ ; X64-LABEL: name: test_anyext_i8
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY %dil
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s8)
+ ; X64: %eax = COPY [[ANYEXT]](s32)
+ ; X64: RET 0, implicit %eax
%0(s8) = COPY %dil
%1(s32) = G_ANYEXT %0(s8)
%eax = COPY %1(s32)
@@ -491,21 +571,26 @@ body: |
...
---
name: test_anyext_i16
-# ALL-LABEL: name: test_anyext_i16
alignment: 4
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
-# ALL: %0:_(s16) = COPY %di
-# ALL-NEXT: %1:_(s32) = G_ANYEXT %0(s16)
-# ALL-NEXT: %eax = COPY %1(s32)
-# ALL-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi
+ ; X32-LABEL: name: test_anyext_i16
+ ; X32: [[COPY:%[0-9]+]]:_(s16) = COPY %di
+ ; X32: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s16)
+ ; X32: %eax = COPY [[ANYEXT]](s32)
+ ; X32: RET 0, implicit %eax
+ ; X64-LABEL: name: test_anyext_i16
+ ; X64: [[COPY:%[0-9]+]]:_(s16) = COPY %di
+ ; X64: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s16)
+ ; X64: %eax = COPY [[ANYEXT]](s32)
+ ; X64: RET 0, implicit %eax
%0(s16) = COPY %di
%1(s32) = G_ANYEXT %0(s16)
%eax = COPY %1(s32)
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-gep.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-gep.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-gep.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-gep.mir Tue Nov 14 14:42:19 2017
@@ -2,22 +2,22 @@
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
--- |
- define void @test_gep_i8() {
+ define void @test_gep_i8(i8* %addr) {
%arrayidx = getelementptr i32, i32* undef, i8 5
ret void
}
- define void @test_gep_i16() {
+ define void @test_gep_i16(i8* %addr) {
%arrayidx = getelementptr i32, i32* undef, i16 5
ret void
}
- define void @test_gep_i32() {
+ define void @test_gep_i32(i8* %addr) {
%arrayidx = getelementptr i32, i32* undef, i32 5
ret void
}
- define void @test_gep_i64() {
+ define void @test_gep_i64(i8* %addr) {
%arrayidx = getelementptr i32, i32* undef, i64 5
ret void
}
@@ -36,10 +36,12 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 20
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s8)
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[SEXT]](s32)
+ ; CHECK: G_STORE [[GEP]](p0), [[DEF]](p0) :: (store 1 into %ir.addr)
; CHECK: RET 0
%0(p0) = IMPLICIT_DEF
%1(s8) = G_CONSTANT i8 20
%2(p0) = G_GEP %0, %1(s8)
+ G_STORE %2, %0 :: (store 1 into %ir.addr)
RET 0
...
---
@@ -56,10 +58,12 @@ body: |
; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 20
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C]](s16)
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[SEXT]](s32)
+ ; CHECK: G_STORE [[GEP]](p0), [[DEF]](p0) :: (store 1 into %ir.addr)
; CHECK: RET 0
%0(p0) = IMPLICIT_DEF
%1(s16) = G_CONSTANT i16 20
%2(p0) = G_GEP %0, %1(s16)
+ G_STORE %2, %0 :: (store 1 into %ir.addr)
RET 0
...
---
@@ -75,10 +79,12 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C]](s32)
+ ; CHECK: G_STORE [[GEP]](p0), [[DEF]](p0) :: (store 1 into %ir.addr)
; CHECK: RET 0
%0(p0) = IMPLICIT_DEF
%1(s32) = G_CONSTANT i32 20
%2(p0) = G_GEP %0, %1(s32)
+ G_STORE %2, %0 :: (store 1 into %ir.addr)
RET 0
...
---
@@ -94,9 +100,11 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 20
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C]](s64)
+ ; CHECK: G_STORE [[GEP]](p0), [[DEF]](p0) :: (store 1 into %ir.addr)
; CHECK: RET 0
%0(p0) = IMPLICIT_DEF
%1(s64) = G_CONSTANT i64 20
%2(p0) = G_GEP %0, %1(s64)
+ G_STORE %2, %0 :: (store 1 into %ir.addr)
RET 0
...
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-memop-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-memop-scalar.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-memop-scalar.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-memop-scalar.mir Tue Nov 14 14:42:19 2017
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
@@ -12,7 +13,6 @@
...
---
name: test_memop_s8tos32
-# ALL-LABEL: name: test_memop_s8tos32
alignment: 4
legalized: false
regBankSelected: false
@@ -28,28 +28,40 @@ registers:
- { id: 8, class: _, preferred-register: '' }
- { id: 9, class: _, preferred-register: '' }
- { id: 10, class: _, preferred-register: '' }
-# ALL: %0:_(p0) = IMPLICIT_DEF
-# ALL-NEXT: %11:_(s8) = G_LOAD %0(p0) :: (load 1)
-# ALL-NEXT: %9:_(s1) = G_TRUNC %11(s8)
-# ALL-NEXT: %1:_(s8) = G_LOAD %0(p0) :: (load 1)
-# ALL-NEXT: %2:_(s16) = G_LOAD %0(p0) :: (load 2)
-# ALL-NEXT: %3:_(s32) = G_LOAD %0(p0) :: (load 4)
-# ALL-NEXT: %4:_(p0) = G_LOAD %0(p0) :: (load 8)
-# ALL-NEXT: %10:_(s1) = IMPLICIT_DEF
-# ALL-NEXT: %12:_(s8) = G_ZEXT %10(s1)
-# ALL-NEXT: G_STORE %12(s8), %0(p0) :: (store 1)
-# ALL-NEXT: %5:_(s8) = IMPLICIT_DEF
-# ALL-NEXT: G_STORE %5(s8), %0(p0) :: (store 1)
-# ALL-NEXT: %6:_(s16) = IMPLICIT_DEF
-# ALL-NEXT: G_STORE %6(s16), %0(p0) :: (store 2)
-# ALL-NEXT: %7:_(s32) = IMPLICIT_DEF
-# ALL-NEXT: G_STORE %7(s32), %0(p0) :: (store 4)
-# ALL-NEXT: %8:_(p0) = IMPLICIT_DEF
-# ALL-NEXT: G_STORE %8(p0), %0(p0) :: (store 8)
body: |
bb.1 (%ir-block.0):
liveins: %rdi
+ ; X64-LABEL: name: test_memop_s8tos32
+ ; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+ ; X64: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
+ ; X64: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
+ ; X64: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[DEF]](p0) :: (load 2)
+ ; X64: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4)
+ ; X64: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load 8)
+ ; X64: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY [[LOAD]](s8)
+ ; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY]], [[C]]
+ ; X64: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
+ ; X64: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store 1)
+ ; X64: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store 2)
+ ; X64: G_STORE [[LOAD3]](s32), [[DEF]](p0) :: (store 4)
+ ; X64: G_STORE [[LOAD4]](p0), [[DEF]](p0) :: (store 8)
+ ; X32-LABEL: name: test_memop_s8tos32
+ ; X32: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+ ; X32: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
+ ; X32: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
+ ; X32: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[DEF]](p0) :: (load 2)
+ ; X32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4)
+ ; X32: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load 8)
+ ; X32: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY [[LOAD]](s8)
+ ; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY]], [[C]]
+ ; X32: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
+ ; X32: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store 1)
+ ; X32: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store 2)
+ ; X32: G_STORE [[LOAD3]](s32), [[DEF]](p0) :: (store 4)
+ ; X32: G_STORE [[LOAD4]](p0), [[DEF]](p0) :: (store 8)
%0(p0) = IMPLICIT_DEF
%9(s1) = G_LOAD %0(p0) :: (load 1)
%1(s8) = G_LOAD %0(p0) :: (load 1)
@@ -57,20 +69,14 @@ body: |
%3(s32) = G_LOAD %0(p0) :: (load 4)
%4(p0) = G_LOAD %0(p0) :: (load 8)
- %10(s1) = IMPLICIT_DEF
- G_STORE %10, %0 :: (store 1)
- %5(s8) = IMPLICIT_DEF
- G_STORE %5, %0 :: (store 1)
- %6(s16) = IMPLICIT_DEF
- G_STORE %6, %0 :: (store 2)
- %7(s32) = IMPLICIT_DEF
- G_STORE %7, %0 :: (store 4)
- %8(p0) = IMPLICIT_DEF
- G_STORE %8, %0 :: (store 8)
+ G_STORE %9, %0 :: (store 1)
+ G_STORE %1, %0 :: (store 1)
+ G_STORE %2, %0 :: (store 2)
+ G_STORE %3, %0 :: (store 4)
+ G_STORE %4, %0 :: (store 8)
...
---
name: test_memop_s64
-# ALL-LABEL: name: test_memop_s64
alignment: 4
legalized: false
regBankSelected: false
@@ -79,31 +85,28 @@ registers:
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
liveins:
-# X64: %0:_(p0) = IMPLICIT_DEF
-# X64-NEXT: %1:_(s64) = G_LOAD %0(p0) :: (load 8)
-# X64-NEXT: %2:_(s64) = IMPLICIT_DEF
-# X64-NEXT: G_STORE %2(s64), %0(p0) :: (store 8)
#
-# X32: %0:_(p0) = IMPLICIT_DEF
-# X32-NEXT: %3:_(s32) = G_LOAD %0(p0) :: (load 8)
-# X32-NEXT: %6:_(s32) = G_CONSTANT i32 4
-# X32-NEXT: %5:_(p0) = G_GEP %0, %6(s32)
-# X32-NEXT: %4:_(s32) = G_LOAD %5(p0) :: (load 8)
-# X32-NEXT: %1:_(s64) = G_MERGE_VALUES %3(s32), %4(s32)
-# X32-NEXT: %2:_(s64) = IMPLICIT_DEF
-# X32-NEXT: %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %2(s64)
-# X32-NEXT: G_STORE %7(s32), %0(p0) :: (store 8)
-# X32-NEXT: %10:_(s32) = G_CONSTANT i32 4
-# X32-NEXT: %9:_(p0) = G_GEP %0, %10(s32)
-# X32-NEXT: G_STORE %8(s32), %9(p0) :: (store 8)
body: |
bb.1 (%ir-block.0):
liveins: %rdi
+ ; X64-LABEL: name: test_memop_s64
+ ; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+ ; X64: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[DEF]](p0) :: (load 8)
+ ; X64: G_STORE [[LOAD]](s64), [[DEF]](p0) :: (store 8)
+ ; X32-LABEL: name: test_memop_s64
+ ; X32: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+ ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 8)
+ ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C]](s32)
+ ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p0) :: (load 8)
+ ; X32: G_STORE [[LOAD]](s32), [[DEF]](p0) :: (store 8)
+ ; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C1]](s32)
+ ; X32: G_STORE [[LOAD1]](s32), [[GEP1]](p0) :: (store 8)
%0(p0) = IMPLICIT_DEF
%1(s64) = G_LOAD %0(p0) :: (load 8)
- %2(s64) = IMPLICIT_DEF
- G_STORE %2, %0 :: (store 8)
+ G_STORE %1, %0 :: (store 8)
...
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir Tue Nov 14 14:42:19 2017
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
--- |
@@ -21,7 +22,6 @@
...
---
name: test_mul_i1
-# CHECK-LABEL: name: test_mul_i1
alignment: 4
legalized: false
regBankSelected: false
@@ -29,45 +29,46 @@ registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
- { id: 2, class: _, preferred-register: '' }
-# CHECK: %0:_(s32) = COPY %edx
-# CHECK-NEXT: %3:_(s8) = G_TRUNC %0(s32)
-# CHECK-NEXT: %4:_(s8) = G_TRUNC %0(s32)
-# CHECK-NEXT: %5:_(s8) = G_MUL %3, %4
-# CHECK-NEXT: %2:_(s1) = G_TRUNC %5(s8)
-# CHECK-NEXT: RET 0
body: |
bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_mul_i1
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %edx
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[MUL:%[0-9]+]]:_(s8) = G_MUL [[TRUNC]], [[TRUNC1]]
+ ; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
+ ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[MUL]](s8)
+ ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY1]], [[C]]
+ ; CHECK: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
+ ; CHECK: RET 0
%0(s32) = COPY %edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_MUL %1, %1
+ %3:_(p0) = G_IMPLICIT_DEF
+ G_STORE %2, %3 :: (store 1)
RET 0
...
---
name: test_mul_i16
-# CHECK-LABEL: name: test_mul_i16
alignment: 4
legalized: false
regBankSelected: false
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' }
-# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# CHECK: body: |
-# CHECK-NEXT: bb.0 (%ir-block.0):
-# CHECK-NEXT: %0:_(s16) = COPY %di
-# CHECK-NEXT: %1:_(s16) = COPY %si
-# CHECK-NEXT: %2:_(s16) = G_MUL %0, %1
-# CHECK-NEXT: %ax = COPY %2(s16)
-# CHECK-NEXT: RET 0, implicit %ax
body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
+ ; CHECK-LABEL: name: test_mul_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY %di
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY %si
+ ; CHECK: [[MUL:%[0-9]+]]:_(s16) = G_MUL [[COPY]], [[COPY1]]
+ ; CHECK: %ax = COPY [[MUL]](s16)
+ ; CHECK: RET 0, implicit %ax
%0(s16) = COPY %di
%1(s16) = COPY %si
%2(s16) = G_MUL %0, %1
@@ -77,29 +78,23 @@ body: |
...
---
name: test_mul_i32
-# CHECK-LABEL: name: test_mul_i32
alignment: 4
legalized: false
regBankSelected: false
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' }
-# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# CHECK: body: |
-# CHECK-NEXT: bb.0 (%ir-block.0):
-# CHECK-NEXT: %0:_(s32) = COPY %edi
-# CHECK-NEXT: %1:_(s32) = COPY %esi
-# CHECK-NEXT: %2:_(s32) = G_MUL %0, %1
-# CHECK-NEXT: %eax = COPY %2(s32)
-# CHECK-NEXT: RET 0, implicit %eax
body: |
bb.1 (%ir-block.0):
liveins: %edi, %esi
+ ; CHECK-LABEL: name: test_mul_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY %edi
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY %esi
+ ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
+ ; CHECK: %eax = COPY [[MUL]](s32)
+ ; CHECK: RET 0, implicit %eax
%0(s32) = COPY %edi
%1(s32) = COPY %esi
%2(s32) = G_MUL %0, %1
@@ -109,29 +104,23 @@ body: |
...
---
name: test_mul_i64
-# CHECK-LABEL: name: test_mul_i64
alignment: 4
legalized: false
regBankSelected: false
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' }
-# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
-# CHECK: body: |
-# CHECK-NEXT: bb.0 (%ir-block.0):
-# CHECK-NEXT: %0:_(s64) = COPY %rdi
-# CHECK-NEXT: %1:_(s64) = COPY %rsi
-# CHECK-NEXT: %2:_(s64) = G_MUL %0, %1
-# CHECK-NEXT: %rax = COPY %2(s64)
-# CHECK-NEXT: RET 0, implicit %rax
body: |
bb.1 (%ir-block.0):
liveins: %rdi, %rsi
+ ; CHECK-LABEL: name: test_mul_i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY %rdi
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY %rsi
+ ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]]
+ ; CHECK: %rax = COPY [[MUL]](s64)
+ ; CHECK: RET 0, implicit %rax
%0(s64) = COPY %rdi
%1(s64) = COPY %rsi
%2(s64) = G_MUL %0, %1
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir Tue Nov 14 14:42:19 2017
@@ -45,11 +45,17 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s8) = G_OR [[TRUNC]], [[TRUNC1]]
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[OR]](s8)
+ ; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
+ ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[OR]](s8)
+ ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY1]], [[C]]
+ ; CHECK: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
; CHECK: RET 0
%0(s32) = COPY %edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_OR %1, %1
+ %3:_(p0) = G_IMPLICIT_DEF
+ G_STORE %2, %3 :: (store 1)
RET 0
...
---
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-phi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-phi.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-phi.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-phi.mir Tue Nov 14 14:42:19 2017
@@ -159,9 +159,7 @@ body: |
; ALL: [[ANYEXT1:%[0-9]+]]:_(s8) = G_ANYEXT [[COPY2]](s1)
; ALL: bb.3.cond.end:
; ALL: [[PHI:%[0-9]+]]:_(s8) = G_PHI [[ANYEXT]](s8), %bb.1.cond.true, [[ANYEXT1]](s8), %bb.2.cond.false
- ; ALL: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[PHI]](s8)
- ; ALL: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[TRUNC]](s1)
- ; ALL: %al = COPY [[ZEXT]](s8)
+ ; ALL: %al = COPY
; ALL: RET 0, implicit %al
bb.1.entry:
successors: %bb.2.cond.true(0x40000000), %bb.3.cond.false(0x40000000)
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir Tue Nov 14 14:42:19 2017
@@ -43,6 +43,7 @@ body: |
%0(<16 x s8>) = IMPLICIT_DEF
%1(<16 x s8>) = IMPLICIT_DEF
%2(<16 x s8>) = G_SUB %0, %1
+ %xmm0 = COPY %2
RET 0
...
@@ -67,6 +68,7 @@ body: |
%0(<8 x s16>) = IMPLICIT_DEF
%1(<8 x s16>) = IMPLICIT_DEF
%2(<8 x s16>) = G_SUB %0, %1
+ %xmm0 = COPY %2
RET 0
...
@@ -91,6 +93,7 @@ body: |
%0(<4 x s32>) = IMPLICIT_DEF
%1(<4 x s32>) = IMPLICIT_DEF
%2(<4 x s32>) = G_SUB %0, %1
+ %xmm0 = COPY %2
RET 0
...
@@ -115,6 +118,7 @@ body: |
%0(<2 x s64>) = IMPLICIT_DEF
%1(<2 x s64>) = IMPLICIT_DEF
%2(<2 x s64>) = G_SUB %0, %1
+ %xmm0 = COPY %2
RET 0
...
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir Tue Nov 14 14:42:19 2017
@@ -44,6 +44,7 @@ body: |
%0(<32 x s8>) = IMPLICIT_DEF
%1(<32 x s8>) = IMPLICIT_DEF
%2(<32 x s8>) = G_SUB %0, %1
+ %ymm0 = COPY %2
RET 0
...
@@ -68,6 +69,7 @@ body: |
%0(<16 x s16>) = IMPLICIT_DEF
%1(<16 x s16>) = IMPLICIT_DEF
%2(<16 x s16>) = G_SUB %0, %1
+ %ymm0 = COPY %2
RET 0
...
@@ -92,6 +94,7 @@ body: |
%0(<8 x s32>) = IMPLICIT_DEF
%1(<8 x s32>) = IMPLICIT_DEF
%2(<8 x s32>) = G_SUB %0, %1
+ %ymm0 = COPY %2
RET 0
...
@@ -116,6 +119,7 @@ body: |
%0(<4 x s64>) = IMPLICIT_DEF
%1(<4 x s64>) = IMPLICIT_DEF
%2(<4 x s64>) = G_SUB %0, %1
+ %ymm0 = COPY %2
RET 0
...
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir Tue Nov 14 14:42:19 2017
@@ -44,6 +44,7 @@ body: |
%0(<64 x s8>) = IMPLICIT_DEF
%1(<64 x s8>) = IMPLICIT_DEF
%2(<64 x s8>) = G_SUB %0, %1
+ %zmm0 = COPY %2
RET 0
...
@@ -68,6 +69,7 @@ body: |
%0(<32 x s16>) = IMPLICIT_DEF
%1(<32 x s16>) = IMPLICIT_DEF
%2(<32 x s16>) = G_SUB %0, %1
+ %zmm0 = COPY %2
RET 0
...
@@ -92,6 +94,7 @@ body: |
%0(<16 x s32>) = IMPLICIT_DEF
%1(<16 x s32>) = IMPLICIT_DEF
%2(<16 x s32>) = G_SUB %0, %1
+ %zmm0 = COPY %2
RET 0
...
@@ -116,6 +119,7 @@ body: |
%0(<8 x s64>) = IMPLICIT_DEF
%1(<8 x s64>) = IMPLICIT_DEF
%2(<8 x s64>) = G_SUB %0, %1
+ %zmm0 = COPY %2
RET 0
...
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-sub.mir Tue Nov 14 14:42:19 2017
@@ -28,11 +28,17 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK: [[SUB:%[0-9]+]]:_(s8) = G_SUB [[TRUNC]], [[TRUNC1]]
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[SUB]](s8)
+ ; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
+ ; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[SUB]](s8)
+ ; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY1]], [[C]]
+ ; CHECK: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
; CHECK: RET 0
%0(s32) = COPY %edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_SUB %1, %1
+ %3:_(p0) = G_IMPLICIT_DEF
+ G_STORE %2, %3 :: (store 1)
RET 0
...
---
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-trunc.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-trunc.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-trunc.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-trunc.mir Tue Nov 14 14:42:19 2017
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
--- |
@@ -8,7 +9,6 @@
...
---
name: trunc_check
-# ALL-LABEL: name: trunc_check
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
@@ -16,15 +16,40 @@ registers:
- { id: 3, class: _ }
body: |
bb.1 (%ir-block.0):
+ ; X32-LABEL: name: trunc_check
+ ; X32: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
+ ; X32: [[DEF1:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
+ ; X32: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; X32: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
+ ; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
+ ; X32: G_STORE [[AND]](s8), [[DEF1]](p0) :: (store 1)
+ ; X32: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
+ ; X32: G_STORE [[TRUNC1]](s8), [[DEF1]](p0) :: (store 8)
+ ; X32: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
+ ; X32: G_STORE [[TRUNC2]](s16), [[DEF1]](p0) :: (store 16)
+ ; X32: RET 0
+ ; X64-LABEL: name: trunc_check
+ ; X64: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
+ ; X64: [[DEF1:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
+ ; X64: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+ ; X64: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
+ ; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
+ ; X64: G_STORE [[AND]](s8), [[DEF1]](p0) :: (store 1)
+ ; X64: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
+ ; X64: G_STORE [[TRUNC1]](s8), [[DEF1]](p0) :: (store 8)
+ ; X64: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
+ ; X64: G_STORE [[TRUNC2]](s16), [[DEF1]](p0) :: (store 16)
+ ; X64: RET 0
%0(s32) = IMPLICIT_DEF
- ; ALL: %1:_(s1) = G_TRUNC %0(s32)
%1(s1) = G_TRUNC %0(s32)
+ %4:_(p0) = G_IMPLICIT_DEF
+ G_STORE %1, %4 :: (store 1)
- ; ALL: %2:_(s8) = G_TRUNC %0(s32)
%2(s8) = G_TRUNC %0(s32)
+ G_STORE %2, %4 :: (store 8)
- ; ALL: %3:_(s16) = G_TRUNC %0(s32)
%3(s16) = G_TRUNC %0(s32)
+ G_STORE %3, %4 :: (store 16)
RET 0
...
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-undef.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-undef.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-undef.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-undef.mir Tue Nov 14 14:42:19 2017
@@ -1,29 +1,51 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
---
name: test_implicit_def
-# ALL-LABEL: name: test_implicit_def
registers:
-# X64: %0:_(s1) = G_IMPLICIT_DEF
-# X64-NEXT: %1:_(s8) = G_IMPLICIT_DEF
-# X64-NEXT: %2:_(s16) = G_IMPLICIT_DEF
-# X64-NEXT: %3:_(s32) = G_IMPLICIT_DEF
-# X64-NEXT: %4:_(s64) = G_IMPLICIT_DEF
#
-# X32: %0:_(s1) = G_IMPLICIT_DEF
-# X32-NEXT: %1:_(s8) = G_IMPLICIT_DEF
-# X32-NEXT: %2:_(s16) = G_IMPLICIT_DEF
-# X32-NEXT: %3:_(s32) = G_IMPLICIT_DEF
-# X32-NEXT: %5:_(s32) = G_IMPLICIT_DEF
-# X32-NEXT: %6:_(s32) = G_IMPLICIT_DEF
-# X32-NEXT: %4:_(s64) = G_MERGE_VALUES %5(s32), %6(s32)
body: |
bb.0.entry:
liveins:
+ ; X64-LABEL: name: test_implicit_def
+ ; X64: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
+ ; X64: [[DEF1:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
+ ; X64: G_STORE [[DEF1]](s8), [[DEF]](p0) :: (store 1)
+ ; X64: [[DEF2:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
+ ; X64: G_STORE [[DEF2]](s8), [[DEF]](p0) :: (store 8)
+ ; X64: [[DEF3:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; X64: G_STORE [[DEF3]](s16), [[DEF]](p0) :: (store 16)
+ ; X64: [[DEF4:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; X64: G_STORE [[DEF4]](s32), [[DEF]](p0) :: (store 32)
+ ; X64: [[DEF5:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+ ; X64: G_STORE [[DEF5]](s64), [[DEF]](p0) :: (store 64)
+ ; X32-LABEL: name: test_implicit_def
+ ; X32: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
+ ; X32: [[DEF1:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
+ ; X32: G_STORE [[DEF1]](s8), [[DEF]](p0) :: (store 1)
+ ; X32: [[DEF2:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
+ ; X32: G_STORE [[DEF2]](s8), [[DEF]](p0) :: (store 8)
+ ; X32: [[DEF3:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; X32: G_STORE [[DEF3]](s16), [[DEF]](p0) :: (store 16)
+ ; X32: [[DEF4:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; X32: G_STORE [[DEF4]](s32), [[DEF]](p0) :: (store 32)
+ ; X32: [[DEF5:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; X32: [[DEF6:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; X32: G_STORE [[DEF5]](s32), [[DEF]](p0) :: (store 64)
+ ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C]](s32)
+ ; X32: G_STORE [[DEF6]](s32), [[GEP]](p0) :: (store 64)
+ %5:_(p0) = G_IMPLICIT_DEF
%0:_(s1) = G_IMPLICIT_DEF
+ G_STORE %0, %5 ::(store 1)
%1:_(s8) = G_IMPLICIT_DEF
+ G_STORE %1, %5 ::(store 8)
%2:_(s16) = G_IMPLICIT_DEF
+ G_STORE %2, %5 ::(store 16)
%3:_(s32) = G_IMPLICIT_DEF
+ G_STORE %3, %5 ::(store 32)
%4:_(s64) = G_IMPLICIT_DEF
+ G_STORE %4, %5 ::(store 64)
...
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir Tue Nov 14 14:42:19 2017
@@ -45,11 +45,12 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[TRUNC]], [[TRUNC1]]
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[XOR]](s8)
; CHECK: RET 0
%0(s32) = COPY %edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_XOR %1, %1
+ %3:_(p0) = G_IMPLICIT_DEF
+ G_STORE %2, %3 ::(store 1)
RET 0
...
---
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/or-scalar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/or-scalar.ll?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/or-scalar.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/or-scalar.ll Tue Nov 14 14:42:19 2017
@@ -7,6 +7,7 @@ define i32 @test_or_i1(i32 %arg1, i32 %a
; ALL-NEXT: cmpl %esi, %edi
; ALL-NEXT: sete %al
; ALL-NEXT: orb %al, %al
+; ALL-NEXT: movzbl %al, %eax
; ALL-NEXT: andl $1, %eax
; ALL-NEXT: retq
%c = icmp eq i32 %arg1, %arg2
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/sub-scalar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/sub-scalar.ll?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/sub-scalar.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/sub-scalar.ll Tue Nov 14 14:42:19 2017
@@ -45,8 +45,8 @@ define i32 @test_sub_i1(i32 %arg1, i32 %
; X64-LABEL: test_sub_i1:
; X64: # BB#0:
; X64-NEXT: subb %sil, %dil
-; X64-NEXT: andl $1, %edi
-; X64-NEXT: movl %edi, %eax
+; X64-NEXT: movzbl %dil, %eax
+; X64-NEXT: andl $1, %eax
; X64-NEXT: retq
%a1 = trunc i32 %arg1 to i1
%a2 = trunc i32 %arg2 to i1
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-fallback.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-fallback.ll?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-fallback.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-fallback.ll Tue Nov 14 14:42:19 2017
@@ -8,7 +8,7 @@
; the fallback path.
; Check that we fallback on invoke translation failures.
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg1<def>(s80) = G_FCONSTANT x86_fp80 0xK4002A000000000000000
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: G_STORE %vreg1, %vreg0; mem:ST10[%ptr](align=16) (in function: test_x86_fp80_dump)
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for test_x86_fp80_dump
; FALLBACK-WITH-REPORT-OUT-LABEL: test_x86_fp80_dump:
define void @test_x86_fp80_dump(x86_fp80* %ptr){
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/xor-scalar.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/xor-scalar.ll?rev=318210&r1=318209&r2=318210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/xor-scalar.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/xor-scalar.ll Tue Nov 14 14:42:19 2017
@@ -7,6 +7,7 @@ define i32 @test_xor_i1(i32 %arg1, i32 %
; ALL-NEXT: cmpl %esi, %edi
; ALL-NEXT: sete %al
; ALL-NEXT: xorb %al, %al
+; ALL-NEXT: movzbl %al, %eax
; ALL-NEXT: andl $1, %eax
; ALL-NEXT: retq
%c = icmp eq i32 %arg1, %arg2
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