[llvm] r318146 - [ARM GlobalISel] Remove C++ code for G_CONSTANT
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 14 03:20:32 PST 2017
Author: rovka
Date: Tue Nov 14 03:20:32 2017
New Revision: 318146
URL: http://llvm.org/viewvc/llvm-project?rev=318146&view=rev
Log:
[ARM GlobalISel] Remove C++ code for G_CONSTANT
Get rid of the handwritten instruction selector code for handling
G_CONSTANT. This code wasn't checking all the preconditions correctly
anyway, so it's better to leave it to TableGen, which can handle at
least some cases correctly (e.g. MOVi, MOVi16, folding into binary
operations). Also add tests to cover those cases.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll
Modified: llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp?rev=318146&r1=318145&r2=318146&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp Tue Nov 14 03:20:32 2017
@@ -796,28 +796,6 @@ bool ARMInstructionSelector::select(Mach
I.setDesc(TII.get(ARM::ADDri));
MIB.addImm(0).add(predOps(ARMCC::AL)).add(condCodeOp());
break;
- case G_CONSTANT: {
- unsigned Reg = I.getOperand(0).getReg();
-
- if (!validReg(MRI, Reg, 32, ARM::GPRRegBankID))
- return false;
-
- I.setDesc(TII.get(ARM::MOVi));
- MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
-
- auto &Val = I.getOperand(1);
- if (Val.isCImm()) {
- if (Val.getCImm()->getBitWidth() > 32)
- return false;
- Val.ChangeToImmediate(Val.getCImm()->getZExtValue());
- }
-
- if (!Val.isImm()) {
- return false;
- }
-
- break;
- }
case G_GLOBAL_VALUE:
return selectGlobal(MIB, MRI);
case G_STORE:
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=318146&r1=318145&r2=318146&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Tue Nov 14 03:20:32 2017
@@ -8,6 +8,8 @@
define void @test_trunc_and_anyext_s16() { ret void }
define void @test_add_s32() { ret void }
+ define void @test_add_fold_imm_s32() { ret void }
+ define void @test_add_no_fold_imm_s32() #3 { ret void }
define void @test_fadd_s32() #0 { ret void }
define void @test_fadd_s64() #0 { ret void }
@@ -51,6 +53,7 @@
attributes #0 = { "target-features"="+vfp2,-neonfp" }
attributes #1 = { "target-features"="+v6" }
attributes #2 = { "target-features"="+hwdiv-arm" }
+ attributes #3 = { "target-features"="+v6t2" }
...
---
name: test_trunc_and_zext_s1
@@ -256,6 +259,64 @@ body: |
%2(s32) = G_ADD %0, %1
; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, _, _
+
+ %r0 = COPY %2(s32)
+ ; CHECK: %r0 = COPY [[VREGSUM]]
+
+ BX_RET 14, _, implicit %r0
+ ; CHECK: BX_RET 14, _, implicit %r0
+...
+---
+name: test_add_fold_imm_s32
+# CHECK-LABEL: name: test_add_fold_imm_s32
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(s32) = COPY %r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+
+ %1(s32) = G_CONSTANT i32 255
+ %2(s32) = G_ADD %0, %1
+ ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDri [[VREGX]], 255, 14, _, _
+
+ %r0 = COPY %2(s32)
+ ; CHECK: %r0 = COPY [[VREGSUM]]
+
+ BX_RET 14, _, implicit %r0
+ ; CHECK: BX_RET 14, _, implicit %r0
+...
+---
+name: test_add_no_fold_imm_s32
+# CHECK-LABEL: name: test_add_no_fold_imm_s32
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+ - { id: 2, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(s32) = COPY %r0
+ ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
+
+ %1(s32) = G_CONSTANT i32 65535
+ ; CHECK: [[VREGY:%[0-9]+]]:gpr = MOVi16 65535, 14, _
+
+ %2(s32) = G_ADD %0, %1
+ ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, _, _
%r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGSUM]]
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll?rev=318146&r1=318145&r2=318146&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll Tue Nov 14 03:20:32 2017
@@ -1,7 +1,7 @@
-; RUN: llc -mtriple arm-gnueabi -mattr=+v6,+hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
-; RUN: llc -mtriple arm-gnueabi -mattr=+v6,-hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT-AEABI
-; RUN: llc -mtriple arm-gnu -mattr=+v6,+hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
-; RUN: llc -mtriple arm-gnu -mattr=+v6,-hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT-DEFAULT
+; RUN: llc -mtriple arm-gnueabi -mattr=+v6t2,+hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
+; RUN: llc -mtriple arm-gnueabi -mattr=+v6t2,-hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT-AEABI
+; RUN: llc -mtriple arm-gnu -mattr=+v6t2,+hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,HWDIV
+; RUN: llc -mtriple arm-gnu -mattr=+v6t2,-hwdiv-arm -global-isel %s -o - | FileCheck %s -check-prefixes=CHECK,SOFT-DEFAULT
define arm_aapcscc i32 @test_sdiv_i32(i32 %a, i32 %b) {
; CHECK-LABEL: test_sdiv_i32:
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