[PATCH] D39704: [X86] [CodeGen] Compiler not using SHLD/SHRD instructions when doing double shift pattern combine for 16bit or 8bit arguments (PR35155)

Konstantin Belochapka via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Nov 13 18:53:47 PST 2017


kbelochapka updated this revision to Diff 122764.
kbelochapka edited the summary of this revision.
kbelochapka added a comment.

Updates the fix to support 32bit mode, moved all non 64 bit tests into shift-double.ll


https://reviews.llvm.org/D39704

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/shift-double-x86_64.ll
  test/CodeGen/X86/shift-double.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D39704.122764.patch
Type: text/x-patch
Size: 55714 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20171114/2a1264e8/attachment.bin>


More information about the llvm-commits mailing list