[llvm] r318100 - AMDGPU: Implement computeKnownBitsForTargetNode for mbcnt
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 13 14:55:05 PST 2017
Author: arsenm
Date: Mon Nov 13 14:55:05 2017
New Revision: 318100
URL: http://llvm.org/viewvc/llvm-project?rev=318100&view=rev
Log:
AMDGPU: Implement computeKnownBitsForTargetNode for mbcnt
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
llvm/trunk/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp?rev=318100&r1=318099&r2=318100&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp Mon Nov 13 14:55:05 2017
@@ -4084,6 +4084,20 @@ void AMDGPUTargetLowering::computeKnownB
Known.Zero.setHighBits(32 - MaxValBits);
break;
}
+ case ISD::INTRINSIC_WO_CHAIN: {
+ unsigned IID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+ switch (IID) {
+ case Intrinsic::amdgcn_mbcnt_lo:
+ case Intrinsic::amdgcn_mbcnt_hi: {
+ // These return at most the wavefront size - 1.
+ unsigned Size = Op.getValueType().getSizeInBits();
+ Known.Zero.setHighBits(Size - Subtarget->getWavefrontSizeLog2());
+ break;
+ }
+ default:
+ break;
+ }
+ }
}
}
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h?rev=318100&r1=318099&r2=318100&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUSubtarget.h Mon Nov 13 14:55:05 2017
@@ -228,6 +228,10 @@ public:
return WavefrontSize;
}
+ unsigned getWavefrontSizeLog2() const {
+ return Log2_32(WavefrontSize);
+ }
+
int getLocalMemorySize() const {
return LocalMemorySize;
}
Modified: llvm/trunk/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll?rev=318100&r1=318099&r2=318100&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll Mon Nov 13 14:55:05 2017
@@ -4,8 +4,8 @@ declare i32 @llvm.amdgcn.mbcnt.lo(i32, i
declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0
; SI-LABEL: {{^}}test_array_ptr_calc:
-; SI-DAG: v_mul_lo_i32
-; SI-DAG: v_mul_hi_i32
+; SI-DAG: v_mul_u32_u24
+; SI-DAG: v_mul_hi_u32_u24
; SI: s_endpgm
define amdgpu_kernel void @test_array_ptr_calc(i32 addrspace(1)* noalias %out, [1025 x i32] addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) {
%mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
Modified: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll?rev=318100&r1=318099&r2=318100&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll Mon Nov 13 14:55:05 2017
@@ -14,6 +14,24 @@ main_body:
ret void
}
+; GCN-LABEL: {{^}}mbcnt_lo_known_bits:
+; GCN: v_mbcnt_lo_u32_b32
+; GCN-NOT: and
+define i32 @mbcnt_lo_known_bits(i32 %x, i32 %y) #0 {
+ %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 %x, i32 %y)
+ %mask = and i32 %lo, 63
+ ret i32 %mask
+}
+
+; GCN-LABEL: {{^}}mbcnt_hi_known_bits:
+; GCN: v_mbcnt_hi_u32_b32
+; GCN-NOT: and
+define i32 @mbcnt_hi_known_bits(i32 %x, i32 %y) #0 {
+ %hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 %x, i32 %y)
+ %mask = and i32 %hi, 63
+ ret i32 %mask
+}
+
declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1
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