[llvm] r318068 - [globalisel][tablegen] Add support for extload.

[Daniel Sanders via llvm-commits]

Author: dsanders
Date: Mon Nov 13 10:30:23 2017
New Revision: 318068

URL: http://llvm.org/viewvc/llvm-project?rev=318068&view=rev
Log:
[globalisel][tablegen] Add support for extload.

Modified:
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mir
    llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mir?rev=318068&r1=318067&r2=318068&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-load.mir Mon Nov 13 10:30:23 2017
@@ -33,6 +33,7 @@
 
   define void @sextload_s32_from_s16(i16 *%addr) { ret void }
   define void @zextload_s32_from_s16(i16 *%addr) { ret void }
+  define void @aextload_s32_from_s16(i16 *%addr) { ret void }
 ...
 
 ---
@@ -95,8 +96,7 @@ body:             |
     ; CHECK-LABEL: name: load_s16_gpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
     ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr)
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
-    ; CHECK: %w0 = COPY [[COPY1]]
+    ; CHECK: %w0 = COPY [[LDRHHui]]
     %0(p0) = COPY %x0
     %1(s16) = G_LOAD  %0 :: (load 2 from %ir.addr)
     %2:gpr(s32) = G_ANYEXT %1
@@ -119,8 +119,7 @@ body:             |
     ; CHECK-LABEL: name: load_s8_gpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
     ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1 from %ir.addr)
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
-    ; CHECK: %w0 = COPY [[COPY1]]
+    ; CHECK: %w0 = COPY [[LDRBBui]]
     %0(p0) = COPY %x0
     %1(s8) = G_LOAD  %0 :: (load 1 from %ir.addr)
     %2:gpr(s32) = G_ANYEXT %1
@@ -221,8 +220,7 @@ body:             |
     ; CHECK-LABEL: name: load_gep_64_s16_gpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
     ; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 32 :: (load 2 from %ir.addr)
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
-    ; CHECK: %w0 = COPY [[COPY1]]
+    ; CHECK: %w0 = COPY [[LDRHHui]]
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 64
     %2(p0) = G_GEP %0, %1
@@ -249,8 +247,7 @@ body:             |
     ; CHECK-LABEL: name: load_gep_1_s8_gpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
     ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 1 :: (load 1 from %ir.addr)
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
-    ; CHECK: %w0 = COPY [[COPY1]]
+    ; CHECK: %w0 = COPY [[LDRBBui]]
     %0(p0) = COPY %x0
     %1(s64) = G_CONSTANT i64 1
     %2(p0) = G_GEP %0, %1
@@ -508,3 +505,22 @@ body:             |
     %2:gpr(s32) = G_ZEXT %1
     %w0 = COPY %2(s32)
 ...
+
+---
+name:            aextload_s32_from_s16
+legalized:       true
+regBankSelected: true
+
+body:             |
+  bb.0:
+    liveins: %w0
+
+    ; CHECK-LABEL: name: aextload_s32_from_s16
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
+    ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr)
+    ; CHECK: %w0 = COPY [[T0]]
+    %0:gpr(p0) = COPY %x0
+    %1:gpr(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
+    %2:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %2(s32)
+...

Modified: llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp?rev=318068&r1=318067&r2=318068&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp Mon Nov 13 10:30:23 2017
@@ -3507,11 +3507,12 @@ TreePatternNode *GlobalISelEmitter::fixu
       // must be transformed into:
       //   (sext:[i32] (ld:[i16] [iPTR])<<unindexed>>)
       //
-      // Likewise for zeroext-load.
+      // Likewise for zeroext-load and anyext-load.
 
       std::vector<TreePredicateFn> Predicates;
       bool IsSignExtLoad = false;
       bool IsZeroExtLoad = false;
+      bool IsAnyExtLoad = false;
       Record *MemVT = nullptr;
       for (const auto &P : N->getPredicateFns()) {
         if (P.isLoad() && P.isSignExtLoad()) {
@@ -3522,6 +3523,10 @@ TreePatternNode *GlobalISelEmitter::fixu
           IsZeroExtLoad = true;
           continue;
         }
+        if (P.isLoad() && P.isAnyExtLoad()) {
+          IsAnyExtLoad = true;
+          continue;
+        }
         if (P.isLoad() && P.getMemoryVT()) {
           MemVT = P.getMemoryVT();
           continue;
@@ -3529,12 +3534,13 @@ TreePatternNode *GlobalISelEmitter::fixu
         Predicates.push_back(P);
       }
 
-      if ((IsSignExtLoad || IsZeroExtLoad) && MemVT) {
-        assert(((IsSignExtLoad && !IsZeroExtLoad) ||
-                (!IsSignExtLoad && IsZeroExtLoad)) &&
-               "IsSignExtLoad and IsZeroExtLoad are mutually exclusive");
+      if ((IsSignExtLoad || IsZeroExtLoad || IsAnyExtLoad) && MemVT) {
+        assert((IsSignExtLoad + IsZeroExtLoad + IsAnyExtLoad) == 1 &&
+               "IsSignExtLoad, IsZeroExtLoad, IsAnyExtLoad are mutually exclusive");
         TreePatternNode *Ext = new TreePatternNode(
-            RK.getDef(IsSignExtLoad ? "sext" : "zext"), {N}, 1);
+            RK.getDef(IsSignExtLoad ? "sext"
+                                    : IsZeroExtLoad ? "zext" : "anyext"),
+            {N}, 1);
         Ext->setType(0, N->getType(0));
         N->clearPredicateFns();
         N->setPredicateFns(Predicates);