[PATCH] D39899: [X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule class

[Gadi Haber via Phabricator via llvm-commits]

gadi.haber added a comment.

Note that  WriteALU means 1 cycle latency using  Port 0156

This is true for CBW, CDQE and CWDE.
However, CQO and CDQ do not use port0156 and CWD takes 2 cycles and 2 ports.
See below:

iform: ,                    latency:    ports:
XED_IFORM_CBW      1           0156 
XED_IFORM_CDQE    1            0156 
XED_IFORM_CWDE   1            0156

XED_IFORM_CQO     1             06 
XED_IFORM_CDQ     1             06

XED_IFORM_CWD 2                06, 0156


Repository:
  rL LLVM

https://reviews.llvm.org/D39899