[llvm] r318018 - [X86] Add tests for missed opportunities to fold a 128-bit vector load into vfpclassss and vpfpclasssd.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 12 22:46:46 PST 2017
Author: ctopper
Date: Sun Nov 12 22:46:46 2017
New Revision: 318018
URL: http://llvm.org/viewvc/llvm-project?rev=318018&view=rev
Log:
[X86] Add tests for missed opportunities to fold a 128-bit vector load into vfpclassss and vpfpclasssd.
Modified:
llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics.ll
Modified: llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics.ll?rev=318018&r1=318017&r2=318018&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512dq-intrinsics.ll Sun Nov 12 22:46:46 2017
@@ -396,6 +396,19 @@ define i8 @test_int_x86_avx512_mask_fpcl
ret i8 %res2
}
+define i8 @test_int_x86_avx512_mask_fpclass_sd_load(<2 x double>* %x0ptr) {
+; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_sd_load:
+; CHECK: ## BB#0:
+; CHECK-NEXT: vmovapd (%rdi), %xmm0
+; CHECK-NEXT: vfpclasssd $4, %xmm0, %k0
+; CHECK-NEXT: kmovw %k0, %eax
+; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: retq
+ %x0 = load <2 x double>, <2 x double>* %x0ptr
+ %res = call i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double> %x0, i32 4, i8 -1)
+ ret i8 %res
+}
+
declare i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float>, i32, i8)
define i8 @test_int_x86_avx512_mask_fpclass_ss(<4 x float> %x0, i8 %x1) {
@@ -415,6 +428,19 @@ define i8 @test_int_x86_avx512_mask_fpcl
ret i8 %res2
}
+define i8 @test_int_x86_avx512_mask_fpclass_ss_load(<4 x float>* %x0ptr, i8 %x1) {
+; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ss_load:
+; CHECK: ## BB#0:
+; CHECK-NEXT: vmovaps (%rdi), %xmm0
+; CHECK-NEXT: vfpclassss $4, %xmm0, %k0
+; CHECK-NEXT: kmovw %k0, %eax
+; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
+; CHECK-NEXT: retq
+ %x0 = load <4 x float>, <4 x float>* %x0ptr
+ %res = call i8 @llvm.x86.avx512.mask.fpclass.ss(<4 x float> %x0, i32 4, i8 -1)
+ ret i8 %res
+}
+
declare i16 @llvm.x86.avx512.cvtd2mask.512(<16 x i32>)
define i16 at test_int_x86_avx512_cvtd2mask_512(<16 x i32> %x0) {
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