[PATCH] D39895: [RISCV] MC layer support for the standard RV32D instruction set extension

[Alex Bradbury via Phabricator via llvm-commits]

asb created this revision.
Herald added subscribers: fedor.sergeev, jyknight.

As the FPR32 and FPR64 registers have the same names, use validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an FPR64 when necessary. The rest of this patch is very similar to the RV32F patch.

CCing @dylanmckay and @venkatra, as both AVR and Sparc backends do a similar sort of coercion in validateTargetOperandClass.


https://reviews.llvm.org/D39895

Files:
  lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  lib/Target/RISCV/RISCV.td
  lib/Target/RISCV/RISCVInstrInfo.td
  lib/Target/RISCV/RISCVInstrInfoD.td
  lib/Target/RISCV/RISCVRegisterInfo.td
  lib/Target/RISCV/RISCVSubtarget.h
  test/MC/RISCV/rv32d-invalid.s
  test/MC/RISCV/rv32d-valid.s
  test/MC/RISCV/rv32f-invalid.s

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