[PATCH] D39893: [RISCV] MC layer support for the standard RV32F instruction set extension

[Alex Bradbury via Phabricator via llvm-commits]

asb created this revision.

The most interesting part of this patch to review is probably the handling of rounding mode arguments. Sadly, the RISC-V assembler handles floating point rounding modes as a special "argument" when it would be more consistent to handle them like the atomics, opcode suffixes. This patch supports parsing this optional parameter, using InstAlias to allow parsing these floating point instructions when no rounding mode is specified.

The 'DYN' rounding mode mnemonic is accepted by gas but isn't documented in the released ISA manual. I submitted a PR <https://github.com/riscv/riscv-isa-manual/pull/111> so this will be fixed in the next ISA doc. I've also documented the rounding modes <https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md#floating-point-rounding-modes> in the work in progress RISC-V assembly programmers manual.


https://reviews.llvm.org/D39893

Files:
  lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
  lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h
  lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  lib/Target/RISCV/RISCV.td
  lib/Target/RISCV/RISCVInstrFormats.td
  lib/Target/RISCV/RISCVInstrInfo.td
  lib/Target/RISCV/RISCVInstrInfoF.td
  lib/Target/RISCV/RISCVRegisterInfo.td
  lib/Target/RISCV/RISCVSubtarget.h
  test/MC/RISCV/rv32f-invalid.s
  test/MC/RISCV/rv32f-valid.s
  test/MC/RISCV/rv32i-invalid.s

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