[PATCH] D39845: [TableGen] Give the option of tolerating duplicate register names

[Alex Bradbury via Phabricator via llvm-commits]

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A number of architectures re-use the same register names (e.g. for both 32-bit FPRs and 64-bit FPRs). They are currently unable to use the tablegen'erated MatchRegisterName and MatchRegisterAltName, as tablegen (when built with asserts enabled) will fail.

When the AllowDuplicateRegisterNames in AsmParser is set, duplicated register names will be tolerated. A backend can then coerce registers to the desired register class by (for instance) implementing validateTargetOperandClass.

At least the in-tree Sparc backend could benefit from this, as does RISC-V (single and double precision floating point registers).


https://reviews.llvm.org/D39845

Files:
  include/llvm/TableGen/StringMatcher.h
  include/llvm/Target/Target.td
  lib/TableGen/StringMatcher.cpp
  utils/TableGen/AsmMatcherEmitter.cpp

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