[llvm] r317788 - [RISCV] MC layer support for the standard RV32M instruction set extension
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 9 06:46:31 PST 2017
Author: asb
Date: Thu Nov 9 06:46:30 2017
New Revision: 317788
URL: http://llvm.org/viewvc/llvm-project?rev=317788&view=rev
Log:
[RISCV] MC layer support for the standard RV32M instruction set extension
Added:
llvm/trunk/lib/Target/RISCV/RISCVInstrInfoM.td
llvm/trunk/test/MC/RISCV/rv32m-valid.s
Modified:
llvm/trunk/lib/Target/RISCV/RISCV.td
llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
llvm/trunk/lib/Target/RISCV/RISCVSubtarget.h
llvm/trunk/test/MC/RISCV/rv32i-invalid.s
Modified: llvm/trunk/lib/Target/RISCV/RISCV.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCV.td?rev=317788&r1=317787&r2=317788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCV.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCV.td Thu Nov 9 06:46:30 2017
@@ -13,11 +13,16 @@ include "llvm/Target/Target.td"
// RISC-V subtarget features and instruction predicates.
//===----------------------------------------------------------------------===//
-def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true",
- "Implements RV64">;
+def FeatureStdExtM : SubtargetFeature<"m", "HasStdExtM", "true",
+ "'M' (Integer Multiplication and Division)">;
+def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
+ AssemblerPredicate<"FeatureStdExtM">;
-def RV64 : HwMode<"+64bit">;
-def RV32 : HwMode<"-64bit">;
+def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true",
+ "Implements RV64">;
+
+def RV64 : HwMode<"+64bit">;
+def RV32 : HwMode<"-64bit">;
//===----------------------------------------------------------------------===//
// Registers, calling conventions, instruction descriptions.
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td?rev=317788&r1=317787&r2=317788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td Thu Nov 9 06:46:30 2017
@@ -399,3 +399,9 @@ def ADJCALLSTACKDOWN : Pseudo<(outs), (i
def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
[(CallSeqEnd timm:$amt1, timm:$amt2)]>;
} // Defs = [X2], Uses = [X2]
+
+//===----------------------------------------------------------------------===//
+// Standard extensions
+//===----------------------------------------------------------------------===//
+
+include "RISCVInstrInfoM.td"
Added: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoM.td?rev=317788&view=auto
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoM.td (added)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoM.td Thu Nov 9 06:46:30 2017
@@ -0,0 +1,28 @@
+//===-- RISCVInstrInfoM.td - RISC-V 'M' instructions -------*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'M', Integer
+// Multiplication and Division instruction set extension.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtM] in {
+def MUL : ALU_rr<0b0000001, 0b000, "mul">;
+def MULH : ALU_rr<0b0000001, 0b001, "mulh">;
+def MULHSU : ALU_rr<0b0000001, 0b010, "mulhsu">;
+def MULHU : ALU_rr<0b0000001, 0b011, "mulhu">;
+def DIV : ALU_rr<0b0000001, 0b100, "div">;
+def DIVU : ALU_rr<0b0000001, 0b101, "divu">;
+def REM : ALU_rr<0b0000001, 0b110, "rem">;
+def REMU : ALU_rr<0b0000001, 0b111, "remu">;
+} // Predicates = [HasStdExtM]
Modified: llvm/trunk/lib/Target/RISCV/RISCVSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVSubtarget.h?rev=317788&r1=317787&r2=317788&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVSubtarget.h (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVSubtarget.h Thu Nov 9 06:46:30 2017
@@ -30,6 +30,7 @@ class StringRef;
class RISCVSubtarget : public RISCVGenSubtargetInfo {
virtual void anchor();
+ bool HasStdExtM;
bool HasRV64 = false;
unsigned XLen = 32;
MVT XLenVT = MVT::i32;
@@ -66,6 +67,7 @@ public:
const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
return &TSInfo;
}
+ bool hasStdExtM() const { return HasStdExtM; }
bool is64Bit() const { return HasRV64; }
MVT getXLenVT() const { return XLenVT; }
unsigned getXLen() const { return XLen; }
Modified: llvm/trunk/test/MC/RISCV/rv32i-invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv32i-invalid.s?rev=317788&r1=317787&r2=317788&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv32i-invalid.s (original)
+++ llvm/trunk/test/MC/RISCV/rv32i-invalid.s Thu Nov 9 06:46:30 2017
@@ -128,3 +128,6 @@ lw a4, a5, 111 # CHECK: :[[@LINE]]:8: er
# Too few operands
ori a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+
+# Instruction not in the base ISA
+mul a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
Added: llvm/trunk/test/MC/RISCV/rv32m-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv32m-valid.s?rev=317788&view=auto
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv32m-valid.s (added)
+++ llvm/trunk/test/MC/RISCV/rv32m-valid.s Thu Nov 9 06:46:30 2017
@@ -0,0 +1,33 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+m -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+m -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+m < %s \
+# RUN: | llvm-objdump -mattr=+m -d - | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+m < %s \
+# RUN: | llvm-objdump -mattr=+m -d - | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: mul a4, ra, s0
+# CHECK: encoding: [0x33,0x87,0x80,0x02]
+mul a4, ra, s0
+# CHECK-INST: mulh ra, zero, zero
+# CHECK: encoding: [0xb3,0x10,0x00,0x02]
+mulh x1, x0, x0
+# CHECK-INST: mulhsu t0, t2, t1
+# CHECK: encoding: [0xb3,0xa2,0x63,0x02]
+mulhsu t0, t2, t1
+# CHECK-INST: mulhu a5, a4, a3
+# CHECK: encoding: [0xb3,0x37,0xd7,0x02]
+mulhu a5, a4, a3
+# CHECK-INST: div s0, s0, s0
+# CHECK: encoding: [0x33,0x44,0x84,0x02]
+div s0, s0, s0
+# CHECK-INST: divu gp, a0, a1
+# CHECK: encoding: [0xb3,0x51,0xb5,0x02]
+divu gp, a0, a1
+# CHECK-INST: rem s2, s2, s8
+# CHECK: encoding: [0x33,0x69,0x89,0x03]
+rem s2, s2, s8
+# CHECK-INST: remu s2, s2, s8
+# CHECK: encoding: [0x33,0x79,0x89,0x03]
+remu x18, x18, x24
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