[PATCH] D39712: [ARM] Add an alias for psr and psr_nzcvq

[Leslie Zhai via Phabricator via llvm-commits]

xiangzhai updated this revision to Diff 122027.
xiangzhai retitled this revision from "[ARM] Add an alias for psr" to "[ARM] Add an alias for psr and psr_nzcvq".
xiangzhai added a comment.

Also add an alias for `psr_nzcvq` about this usecase <https://github.com/jserv/mini-arm-os/blob/master/04-Multitasking/context_switch.S#L12>.


Repository:
  rL LLVM

https://reviews.llvm.org/D39712

Files:
  lib/Target/ARM/ARMSystemRegister.td
  test/MC/ARM/thumb2-mclass.s


Index: test/MC/ARM/thumb2-mclass.s
===================================================================
--- test/MC/ARM/thumb2-mclass.s
+++ test/MC/ARM/thumb2-mclass.s
@@ -21,6 +21,7 @@
         mrs  r0, psp
         mrs  r0, primask
         mrs  r0, control
+        mrs  ip, psr
 
 @ CHECK: mrs	r0, apsr                @ encoding: [0xef,0xf3,0x00,0x80]
 @ CHECK: mrs	r0, iapsr               @ encoding: [0xef,0xf3,0x01,0x80]
@@ -33,6 +34,7 @@
 @ CHECK: mrs	r0, psp                 @ encoding: [0xef,0xf3,0x09,0x80]
 @ CHECK: mrs	r0, primask             @ encoding: [0xef,0xf3,0x10,0x80]
 @ CHECK: mrs	r0, control             @ encoding: [0xef,0xf3,0x14,0x80]
+@ CHECK: mrs    r12, xpsr               @ encoding: [0xef,0xf3,0x03,0x8c]
 
 @------------------------------------------------------------------------------
 @ MSR
@@ -53,6 +55,7 @@
         msr  psp, r0
         msr  primask, r0
         msr  control, r0
+        msr  psr_nzcvq, ip
 
 @ CHECK-V6M: msr	apsr, r0                @ encoding: [0x80,0xf3,0x00,0x88]
 @ CHECK-V6M: msr	apsr, r0                @ encoding: [0x80,0xf3,0x00,0x88]
@@ -77,3 +80,4 @@
 @ CHECK: msr	psp, r0                 @ encoding: [0x80,0xf3,0x09,0x88]
 @ CHECK: msr	primask, r0             @ encoding: [0x80,0xf3,0x10,0x88]
 @ CHECK: msr	control, r0             @ encoding: [0x80,0xf3,0x14,0x88]
+@ CHECK: msr    xpsr_nzcvq, r12         @ encoding: [0x8c,0xf3,0x03,0x88]
Index: lib/Target/ARM/ARMSystemRegister.td
===================================================================
--- lib/Target/ARM/ARMSystemRegister.td
+++ lib/Target/ARM/ARMSystemRegister.td
@@ -63,6 +63,8 @@
 def : MClassSysReg<1,    1,    0,    0x802, "eapsr_nzcvq">;
 def : MClassSysReg<0,    0,    1,    0x803, "xpsr">;
 def : MClassSysReg<1,    1,    0,    0x803, "xpsr_nzcvq">;
+def : MClassSysReg<1,    0,    1,    0x803, "psr">;
+def : MClassSysReg<1,    1,    1,    0x803, "psr_nzcvq">;
 
 def : MClassSysReg<0,    0,    1,    0x805, "ipsr">;
 def : MClassSysReg<0,    0,    1,    0x806, "epsr">;


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