[PATCH] D39400: WIP: [MachineOperand][MIR] Add isRenamable to MachineOperand.

[Geoff Berry via Phabricator via llvm-commits]

gberry updated this revision to Diff 121965.
gberry added a comment.
Herald added a subscriber: nhaehnle.

Update lit tests.


https://reviews.llvm.org/D39400

Files:
  include/llvm/CodeGen/MachineOperand.h
  lib/CodeGen/MIRParser/MILexer.cpp
  lib/CodeGen/MIRParser/MILexer.h
  lib/CodeGen/MIRParser/MIParser.cpp
  lib/CodeGen/MIRParser/MIRParser.cpp
  lib/CodeGen/MIRPrinter.cpp
  lib/CodeGen/MachineInstr.cpp
  lib/CodeGen/MachineVerifier.cpp
  lib/CodeGen/RegAllocFast.cpp
  lib/CodeGen/VirtRegMap.cpp
  test/CodeGen/AArch64/arm64-csldst-mmo.ll
  test/CodeGen/AArch64/arm64-misched-memdep-bug.ll
  test/CodeGen/AArch64/arm64-misched-multimmo.ll
  test/CodeGen/AArch64/falkor-hwpf-fix.mir
  test/CodeGen/AArch64/ldst-opt.mir
  test/CodeGen/AArch64/machine-outliner.mir
  test/CodeGen/AArch64/movimm-wzr.mir
  test/CodeGen/AArch64/reg-scavenge-frame.mir
  test/CodeGen/AMDGPU/insert-skips-kill-uncond.mir
  test/CodeGen/AMDGPU/invert-br-undef-vcc.mir
  test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
  test/CodeGen/AMDGPU/reduce-saveexec.mir
  test/CodeGen/AMDGPU/schedule-regpressure.mir
  test/CodeGen/AMDGPU/shrink-carry.mir
  test/CodeGen/AMDGPU/splitkit.mir
  test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
  test/CodeGen/AMDGPU/syncscopes.ll
  test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
  test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
  test/CodeGen/ARM/ARMLoadStoreDBG.mir
  test/CodeGen/ARM/Windows/vla-cpsr.ll
  test/CodeGen/ARM/dbg-range-extension.mir
  test/CodeGen/ARM/expand-pseudos.mir
  test/CodeGen/ARM/fpoffset_overflow.mir
  test/CodeGen/ARM/load_store_opt_kill.mir
  test/CodeGen/ARM/sched-it-debug-nodes.mir
  test/CodeGen/ARM/thumb1-ldst-opt.ll
  test/CodeGen/ARM/v6-jumptable-clobber.mir
  test/CodeGen/ARM/virtregrewriter-subregliveness.mir
  test/CodeGen/ARM/vldm-liveness.mir
  test/CodeGen/Hexagon/branch-folder-hoist-kills.mir
  test/CodeGen/Hexagon/ifcvt-common-kill.mir
  test/CodeGen/Hexagon/ifcvt-impuse-livein.mir
  test/CodeGen/Hexagon/ifcvt-live-subreg.mir
  test/CodeGen/Hexagon/livephysregs-add-pristines.mir
  test/CodeGen/Hexagon/livephysregs-lane-masks.mir
  test/CodeGen/Hexagon/mux-kill1.mir
  test/CodeGen/Hexagon/mux-kill2.mir
  test/CodeGen/Hexagon/newvaluejump-c4.mir
  test/CodeGen/Hexagon/newvaluejump-kill2.mir
  test/CodeGen/MIR/ARM/ifcvt_diamond_unanalyzable.mir
  test/CodeGen/MIR/ARM/ifcvt_forked_diamond_unanalyzable.mir
  test/CodeGen/MIR/ARM/ifcvt_simple_bad_zero_prob_succ.mir
  test/CodeGen/MIR/ARM/ifcvt_simple_unanalyzable.mir
  test/CodeGen/PowerPC/byval-agg-info.ll
  test/CodeGen/PowerPC/debuginfo-stackarg.ll
  test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
  test/CodeGen/PowerPC/quadint-return.ll
  test/CodeGen/PowerPC/scavenging.mir
  test/CodeGen/X86/eflags-copy-expansion.mir
  test/CodeGen/X86/expand-vr64-gr64-copy.mir
  test/CodeGen/X86/fixup-bw-copy.mir
  test/CodeGen/X86/leaFixup32.mir
  test/CodeGen/X86/leaFixup64.mir
  test/CodeGen/X86/misched-copy.ll
  test/CodeGen/X86/post-ra-sched-with-debug.mir
  test/CodeGen/X86/pr27681.mir
  test/CodeGen/X86/pr28560.ll
  test/CodeGen/X86/remat-phys-dead.ll
  test/CodeGen/X86/scavenger.mir
  test/CodeGen/X86/tail-call-conditional.mir
  test/CodeGen/X86/tail-merge-debugloc.ll
  test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
  test/DebugInfo/MIR/X86/live-debug-values-spill.mir
  test/DebugInfo/MIR/X86/live-debug-values.mir
  test/DebugInfo/MIR/X86/live-debug-vars-unused-arg.mir
  test/DebugInfo/MSP430/sdagsplit-1.ll
  test/DebugInfo/X86/bbjoin.ll
  test/DebugInfo/X86/pr34545.ll
  test/DebugInfo/X86/sdag-salvage-add.ll
  test/DebugInfo/X86/sdagsplit-1.ll

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