[llvm] r317582 - [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.

[Florian Hahn via llvm-commits]

Author: fhahn
Date: Tue Nov  7 07:03:11 2017
New Revision: 317582

URL: http://llvm.org/viewvc/llvm-project?rev=317582&view=rev
Log:
[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.

Patch [4/5] in a series to add assembler/disassembler support for AArch64 SVE unpredicated ADD/SUB instructions.

We add SVE as unsupported feature for CPUs that don't have SVE to prevent errors from scheduler models saying it lacks information for these instructions.

Patch by Sander De Smalen.

Reviewed by: rengolin

Differential Revision: https://reviews.llvm.org/D39090

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td
    llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td
    llvm/trunk/lib/Target/AArch64/AArch64SchedCyclone.td
    llvm/trunk/lib/Target/AArch64/AArch64SchedFalkor.td
    llvm/trunk/lib/Target/AArch64/AArch64SchedKryo.td
    llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td
    llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX.td
    llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX2T99.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td?rev=317582&r1=317581&r2=317582&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedA53.td Tue Nov  7 07:03:11 2017
@@ -26,6 +26,8 @@ def CortexA53Model : SchedMachineModel {
                              // Specification - Instruction Timings"
                              // v 1.0 Spreadsheet
   let CompleteModel = 1;
+
+  list<Predicate> UnsupportedFeatures = [HasSVE];
 }
 
 

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td?rev=317582&r1=317581&r2=317582&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedA57.td Tue Nov  7 07:03:11 2017
@@ -31,6 +31,8 @@ def CortexA57Model : SchedMachineModel {
   // experiments and benchmarking data.
   let LoopMicroOpBufferSize = 16;
   let CompleteModel = 1;
+
+  list<Predicate> UnsupportedFeatures = [HasSVE];
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedCyclone.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedCyclone.td?rev=317582&r1=317581&r2=317582&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedCyclone.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedCyclone.td Tue Nov  7 07:03:11 2017
@@ -18,6 +18,8 @@ def CycloneModel : SchedMachineModel {
   let LoadLatency = 4; // Optimistic load latency.
   let MispredictPenalty = 16; // 14-19 cycles are typical.
   let CompleteModel = 1;
+
+  list<Predicate> UnsupportedFeatures = [HasSVE];
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedFalkor.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedFalkor.td?rev=317582&r1=317581&r2=317582&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedFalkor.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedFalkor.td Tue Nov  7 07:03:11 2017
@@ -23,6 +23,8 @@ def FalkorModel : SchedMachineModel {
   let LoadLatency = 3;         // Optimistic load latency.
   let MispredictPenalty = 11;  // Minimum branch misprediction penalty.
   let CompleteModel = 1;
+
+  list<Predicate> UnsupportedFeatures = [HasSVE];
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedKryo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedKryo.td?rev=317582&r1=317581&r2=317582&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedKryo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedKryo.td Tue Nov  7 07:03:11 2017
@@ -27,6 +27,8 @@ def KryoModel : SchedMachineModel {
   // experiments and benchmarking data.
   let LoopMicroOpBufferSize = 16;
   let CompleteModel = 1;
+
+  list<Predicate> UnsupportedFeatures = [HasSVE];
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td?rev=317582&r1=317581&r2=317582&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td Tue Nov  7 07:03:11 2017
@@ -24,6 +24,8 @@ def ExynosM1Model : SchedMachineModel {
   let LoadLatency           =  4; // Optimistic load cases.
   let MispredictPenalty     = 14; // Minimum branch misprediction penalty.
   let CompleteModel         =  1; // Use the default model otherwise.
+
+  list<Predicate> UnsupportedFeatures = [HasSVE];
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX.td?rev=317582&r1=317581&r2=317582&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX.td Tue Nov  7 07:03:11 2017
@@ -25,6 +25,8 @@ def ThunderXT8XModel : SchedMachineModel
   let MispredictPenalty = 8;  // Branch mispredict penalty.
   let PostRAScheduler = 1;    // Use PostRA scheduler.
   let CompleteModel = 1;
+
+  list<Predicate> UnsupportedFeatures = [HasSVE];
 }
 
 // Modeling each pipeline with BufferSize == 0 since T8X is in-order.

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX2T99.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX2T99.td?rev=317582&r1=317581&r2=317582&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX2T99.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedThunderX2T99.td Tue Nov  7 07:03:11 2017
@@ -25,6 +25,8 @@ def ThunderX2T99Model : SchedMachineMode
   let LoopMicroOpBufferSize =  32;
   let PostRAScheduler       =   1; // Using PostRA sched.
   let CompleteModel         =   1;
+
+  list<Predicate> UnsupportedFeatures = [HasSVE];
 }
 
 // Define the issue ports.