[PATCH] D39087: [AArch64][SVE] Asm: Extend EnforceVectorSubVectorTypeIs to distinguish Scalable Vectors

[Florian Hahn via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL317564: [AArch64][SVE] Asm: Extend EnforceVectorSubVectorTypeIs to distinguish Scalable… (authored by fhahn).

Changed prior to commit:
  https://reviews.llvm.org/D39087?vs=119566&id=121865#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D39087

Files:
  llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp


Index: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
===================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -603,6 +603,11 @@
   auto IsSubVec = [](MVT B, MVT P) -> bool {
     if (!B.isVector() || !P.isVector())
       return false;
+    // Logically a <4 x i32> is a valid subvector of <n x 4 x i32>
+    // but until there are obvious use-cases for this, keep the
+    // types separate.
+    if (B.isScalableVector() != P.isScalableVector())
+      return false;
     if (B.getVectorElementType() != P.getVectorElementType())
       return false;
     return B.getVectorNumElements() < P.getVectorNumElements();


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