[PATCH] D39643: [AMDGPU] Fix assertion due to assuming pointer in default addr space is 32 bit

[Yaxun Liu via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL317476: [AMDGPU] Fix assertion due to assuming pointer in default addr space is 32 bit (authored by yaxunl).

Changed prior to commit:
  https://reviews.llvm.org/D39643?vs=121631&id=121723#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D39643

Files:
  llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/trunk/test/CodeGen/AMDGPU/unsupported-calls.ll


Index: llvm/trunk/test/CodeGen/AMDGPU/unsupported-calls.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/unsupported-calls.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/unsupported-calls.ll
@@ -1,5 +1,5 @@
-; RUN: not llc -march=amdgcn -tailcallopt < %s 2>&1 | FileCheck -check-prefix=GCN %s
-; RUN: not llc -march=r600 -mcpu=cypress -tailcallopt < %s 2>&1 | FileCheck -check-prefix=R600 %s
+; RUN: not llc -march=amdgcn -mtriple=amdgcn---amdgiz -tailcallopt < %s 2>&1 | FileCheck -check-prefix=GCN %s
+; RUN: not llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress -tailcallopt < %s 2>&1 | FileCheck -check-prefix=R600 %s
 
 declare i32 @external_function(i32) nounwind
 
Index: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2134,12 +2134,17 @@
   }
 
   if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Callee)) {
-    // FIXME: Remove this hack for function pointer types.
-    const GlobalValue *GV = GA->getGlobal();
-    assert(Callee.getValueType() == MVT::i32);
-    Callee = DAG.getGlobalAddress(GV, DL, MVT::i64, GA->getOffset(),
-                                  false, GA->getTargetFlags());
+    // FIXME: Remove this hack for function pointer types after removing
+    // support of old address space mapping. In the new address space
+    // mapping the pointer in default address space is 64 bit, therefore
+    // does not need this hack.
+    if (Callee.getValueType() == MVT::i32) {
+      const GlobalValue *GV = GA->getGlobal();
+      Callee = DAG.getGlobalAddress(GV, DL, MVT::i64, GA->getOffset(), false,
+                                    GA->getTargetFlags());
+    }
   }
+  assert(Callee.getValueType() == MVT::i64);
 
   const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
 


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