[PATCH] D39595: [DAGCombine] Refactor ReduceLoadWidth

[Florian Hahn via Phabricator via llvm-commits]

fhahn added a comment.

Removing the unneeded `LoadedVT` seems like a straight-forward NFC and I think it would be worth to submit it for review as an isolated change, as it does not seem related to moving some code to `ReduceLoadWidth`.



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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:7969
 
 /// If the result of a wider load is shifted to right of N  bits and then
 /// truncated to a narrower type and where N is a multiple of number of bits of
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If we support extension using AND,  I think we should also update the comment here.


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:7999
                               VT.getSizeInBits() - N01->getZExtValue());
+  } else if (Opc == ISD::AND) {
+    bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
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I am probably missing something, but I am not sure if I see the real benefit of moving this code here.  It seems the visitAND was the  right place to do it, without requiring additional checks. However, it seems like there is potential to simplify the code in `visitAND`


https://reviews.llvm.org/D39595