[PATCH] D38494: [SCEV] Handling for ICmp occuring in the evolution chain.

[Sanjoy Das via Phabricator via llvm-commits]

sanjoy added inline comments.


================
Comment at: lib/Analysis/ScalarEvolution.cpp:4095
+        BackedgeCond = BI->getCondition();
+        IsPositiveBackedgeCond = BI->getSuccessor(0) == L->getHeader();
+      }
----------------
jbhateja wrote:
> sanjoy wrote:
> > jbhateja wrote:
> > > sanjoy wrote:
> > > > I think you also need to check that the false edge actually leaves the loop.  If both the edges out of the conditional branch branch to the header then this rewrite is not valid.
> > > > 
> > > > (Please also add a test case for the above situation ^).
> > > Can you give a scenario where this can happen ? A latch where both the branches have same desitination header ?  
> > Yes
> Yes ? @sanjoy, Can you provide a scenario/test in HLL where such situation is possible.  
I answered "yes" to your second question -- since that's precisely the situation I'm talking about:

```
define void @foo(i1 %c) {
entry:
  br label %loop

loop:
  br i1 %c, label %loop, label %loop
}
```



https://reviews.llvm.org/D38494