[llvm] r317059 - [X86] Add AVX512 support to X86FastISel::fastMaterializeFloatZero.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 31 17:47:45 PDT 2017
Author: ctopper
Date: Tue Oct 31 17:47:45 2017
New Revision: 317059
URL: http://llvm.org/viewvc/llvm-project?rev=317059&view=rev
Log:
[X86] Add AVX512 support to X86FastISel::fastMaterializeFloatZero.
Modified:
llvm/trunk/lib/Target/X86/X86FastISel.cpp
Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=317059&r1=317058&r2=317059&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Tue Oct 31 17:47:45 2017
@@ -3876,14 +3876,15 @@ unsigned X86FastISel::fastMaterializeFlo
return 0;
// Get opcode and regclass for the given zero.
+ bool HasAVX512 = Subtarget->hasAVX512();
unsigned Opc = 0;
const TargetRegisterClass *RC = nullptr;
switch (VT.SimpleTy) {
default: return 0;
case MVT::f32:
if (X86ScalarSSEf32) {
- Opc = X86::FsFLD0SS;
- RC = &X86::FR32RegClass;
+ Opc = HasAVX512 ? X86::AVX512_FsFLD0SS : X86::FsFLD0SS;
+ RC = HasAVX512 ? &X86::FR32XRegClass : &X86::FR32RegClass;
} else {
Opc = X86::LD_Fp032;
RC = &X86::RFP32RegClass;
@@ -3891,8 +3892,8 @@ unsigned X86FastISel::fastMaterializeFlo
break;
case MVT::f64:
if (X86ScalarSSEf64) {
- Opc = X86::FsFLD0SD;
- RC = &X86::FR64RegClass;
+ Opc = HasAVX512 ? X86::AVX512_FsFLD0SD : X86::FsFLD0SD;
+ RC = HasAVX512 ? &X86::FR64XRegClass : &X86::FR64RegClass;
} else {
Opc = X86::LD_Fp064;
RC = &X86::RFP64RegClass;
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