[llvm] r316902 - [GlobalISel|ARM] : Allow legalizing G_FSUB
Javed Absar via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 30 06:51:56 PDT 2017
Author: javed.absar
Date: Mon Oct 30 06:51:56 2017
New Revision: 316902
URL: http://llvm.org/viewvc/llvm-project?rev=316902&view=rev
Log:
[GlobalISel|ARM] : Allow legalizing G_FSUB
Adding support for VSUB.
Reviewed by: @rovka
Differential Revision: https://reviews.llvm.org/D39261
Modified:
llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
Modified: llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp?rev=316902&r1=316901&r2=316902&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/LegalizerHelper.cpp Mon Oct 30 06:51:56 2017
@@ -91,6 +91,9 @@ static RTLIB::Libcall getRTLibDesc(unsig
case TargetOpcode::G_FADD:
assert((Size == 32 || Size == 64) && "Unsupported size");
return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
+ case TargetOpcode::G_FSUB:
+ assert((Size == 32 || Size == 64) && "Unsupported size");
+ return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
case TargetOpcode::G_FREM:
return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
case TargetOpcode::G_FPOW:
@@ -146,6 +149,7 @@ LegalizerHelper::libcall(MachineInstr &M
break;
}
case TargetOpcode::G_FADD:
+ case TargetOpcode::G_FSUB:
case TargetOpcode::G_FPOW:
case TargetOpcode::G_FREM: {
Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
Modified: llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp?rev=316902&r1=316901&r2=316902&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp Mon Oct 30 06:51:56 2017
@@ -103,8 +103,9 @@ ARMLegalizerInfo::ARMLegalizerInfo(const
setAction({G_ICMP, 1, Ty}, Legal);
if (!ST.useSoftFloat() && ST.hasVFP2()) {
- setAction({G_FADD, s32}, Legal);
- setAction({G_FADD, s64}, Legal);
+ for (unsigned BinOp : {G_FADD, G_FSUB})
+ for (auto Ty : {s32, s64})
+ setAction({BinOp, Ty}, Legal);
setAction({G_LOAD, s64}, Legal);
setAction({G_STORE, s64}, Legal);
@@ -113,8 +114,9 @@ ARMLegalizerInfo::ARMLegalizerInfo(const
setAction({G_FCMP, 1, s32}, Legal);
setAction({G_FCMP, 1, s64}, Legal);
} else {
- for (auto Ty : {s32, s64})
- setAction({G_FADD, Ty}, Libcall);
+ for (unsigned BinOp : {G_FADD, G_FSUB})
+ for (auto Ty : {s32, s64})
+ setAction({BinOp, Ty}, Libcall);
setAction({G_FCMP, s1}, Legal);
setAction({G_FCMP, 1, s32}, Custom);
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=316902&r1=316901&r2=316902&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Mon Oct 30 06:51:56 2017
@@ -242,11 +242,10 @@ ARMRegisterBankInfo::getInstrMapping(con
: &ARM::ValueMappings[ARM::GPR3OpsIdx];
break;
}
- case G_FADD: {
+ case G_FADD:
+ case G_FSUB: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
- assert((Ty.getSizeInBits() == 32 || Ty.getSizeInBits() == 64) &&
- "Unsupported size for G_FADD");
- OperandsMapping = Ty.getSizeInBits() == 64
+ OperandsMapping =Ty.getSizeInBits() == 64
? &ARM::ValueMappings[ARM::DPR3OpsIdx]
: &ARM::ValueMappings[ARM::SPR3OpsIdx];
break;
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=316902&r1=316901&r2=316902&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Mon Oct 30 06:51:56 2017
@@ -12,6 +12,9 @@
define void @test_fadd_s32() #0 { ret void }
define void @test_fadd_s64() #0 { ret void }
+ define void @test_fsub_s32() #0 { ret void }
+ define void @test_fsub_s64() #0 { ret void }
+
define void @test_sub_s32() { ret void }
define void @test_mul_s32() #1 { ret void }
@@ -316,6 +319,66 @@ body: |
%d0 = COPY %2(s64)
; CHECK: %d0 = COPY [[VREGSUM]]
+
+ BX_RET 14, _, implicit %d0
+ ; CHECK: BX_RET 14, _, implicit %d0
+...
+---
+name: test_fsub_s32
+# CHECK-LABEL: name: test_fsub_s32
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: fprb }
+ - { id: 1, class: fprb }
+ - { id: 2, class: fprb }
+body: |
+ bb.0:
+ liveins: %s0, %s1
+
+ %0(s32) = COPY %s0
+ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY %s0
+
+ %1(s32) = COPY %s1
+ ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY %s1
+
+ %2(s32) = G_FSUB %0, %1
+ ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, _
+
+ %s0 = COPY %2(s32)
+ ; CHECK: %s0 = COPY [[VREGSUM]]
+
+ BX_RET 14, _, implicit %s0
+ ; CHECK: BX_RET 14, _, implicit %s0
+...
+---
+name: test_fsub_s64
+# CHECK-LABEL: name: test_fsub_s64
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: fprb }
+ - { id: 1, class: fprb }
+ - { id: 2, class: fprb }
+body: |
+ bb.0:
+ liveins: %d0, %d1
+
+ %0(s64) = COPY %d0
+ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY %d0
+
+ %1(s64) = COPY %d1
+ ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY %d1
+
+ %2(s64) = G_FSUB %0, %1
+ ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, _
+
+ %d0 = COPY %2(s64)
+ ; CHECK: %d0 = COPY [[VREGSUM]]
BX_RET 14, _, implicit %d0
; CHECK: BX_RET 14, _, implicit %d0
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll?rev=316902&r1=316901&r2=316902&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-isel-fp.ll Mon Oct 30 06:51:56 2017
@@ -50,6 +50,23 @@ define arm_aapcscc double @test_add_doub
ret double %r
}
+define arm_aapcscc float @test_sub_float(float %x, float %y) {
+; CHECK-LABEL: test_sub_float:
+; HARD: vsub.f32
+; SOFT-AEABI: bl __aeabi_fsub
+; SOFT-DEFAULT: bl __subsf3
+ %r = fsub float %x, %y
+ ret float %r
+}
+
+define arm_aapcscc double @test_sub_double(double %x, double %y) {
+; CHECK-LABEL: test_sub_double:
+; HARD: vsub.f64
+; SOFT-AEABI: bl __aeabi_dsub
+; SOFT-DEFAULT: bl __subdf3
+ %r = fsub double %x, %y
+ ret double %r
+}
define arm_aapcs_vfpcc i32 @test_cmp_float_ogt(float %x, float %y) {
; CHECK-LABEL: test_cmp_float_ogt
; HARD: vcmp.f32
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir?rev=316902&r1=316901&r2=316902&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir Mon Oct 30 06:51:56 2017
@@ -11,6 +11,9 @@
define void @test_fadd_float() { ret void }
define void @test_fadd_double() { ret void }
+ define void @test_fsub_float() { ret void }
+ define void @test_fsub_double() { ret void }
+
define void @test_fcmp_true_s32() { ret void }
define void @test_fcmp_false_s32() { ret void }
@@ -323,6 +326,93 @@ body: |
; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
%7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
%r0 = COPY %7(s32)
+ %r1 = COPY %8(s32)
+ BX_RET 14, _, implicit %r0, implicit %r1
+...
+---
+name: test_fsub_float
+# CHECK-LABEL: name: test_fsub_float
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1
+
+ ; CHECK-DAG: [[X:%[0-9]+]]:_(s32) = COPY %r0
+ ; CHECK-DAG: [[Y:%[0-9]+]]:_(s32) = COPY %r1
+ %0(s32) = COPY %r0
+ %1(s32) = COPY %r1
+ ; HARD: [[R:%[0-9]+]]:_(s32) = G_FSUB [[X]], [[Y]]
+ ; SOFT-NOT: G_FSUB
+ ; SOFT: ADJCALLSTACKDOWN
+ ; SOFT-DAG: %r0 = COPY [[X]]
+ ; SOFT-DAG: %r1 = COPY [[Y]]
+ ; SOFT-AEABI: BL $__aeabi_fsub, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
+ ; SOFT-DEFAULT: BL $__subsf3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0
+ ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY %r0
+ ; SOFT: ADJCALLSTACKUP
+ ; SOFT-NOT: G_FSUB
+ %2(s32) = G_FSUB %0, %1
+ ; CHECK: %r0 = COPY [[R]]
+ %r0 = COPY %2(s32)
+ BX_RET 14, _, implicit %r0
+...
+---
+name: test_fsub_double
+# CHECK-LABEL: name: test_fsub_double
+legalized: false
+# CHECK: legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
+ - { id: 6, class: _ }
+ - { id: 7, class: _ }
+ - { id: 8, class: _ }
+body: |
+ bb.0:
+ liveins: %r0, %r1, %r2, %r3
+
+ ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY %r0
+ ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY %r1
+ ; CHECK-DAG: [[Y0:%[0-9]+]]:_(s32) = COPY %r2
+ ; CHECK-DAG: [[Y1:%[0-9]+]]:_(s32) = COPY %r3
+ %0(s32) = COPY %r0
+ %1(s32) = COPY %r1
+ %2(s32) = COPY %r2
+ %3(s32) = COPY %r3
+ ; HARD-DAG: [[X:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[X0]]
+ ; HARD-DAG: [[Y:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[Y0]]
+ %4(s64) = G_MERGE_VALUES %0(s32), %1(s32)
+ %5(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+ ; HARD: [[R:%[0-9]+]]:_(s64) = G_FSUB [[X]], [[Y]]
+ ; SOFT-NOT: G_FSUB
+ ; SOFT: ADJCALLSTACKDOWN
+ ; SOFT-DAG: %r{{[0-1]}} = COPY [[X0]]
+ ; SOFT-DAG: %r{{[0-1]}} = COPY [[X1]]
+ ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y0]]
+ ; SOFT-DAG: %r{{[2-3]}} = COPY [[Y1]]
+ ; SOFT-AEABI: BL $__aeabi_dsub, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
+ ; SOFT-DEFAULT: BL $__subdf3, {{.*}}, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1
+ ; SOFT: ADJCALLSTACKUP
+ ; SOFT-NOT: G_FSUB
+ %6(s64) = G_FSUB %4, %5
+ ; HARD-DAG: G_UNMERGE_VALUES [[R]](s64)
+ %7(s32),%8(s32) = G_UNMERGE_VALUES %6(s64)
+ %r0 = COPY %7(s32)
%r1 = COPY %8(s32)
BX_RET 14, _, implicit %r0, implicit %r1
...
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=316902&r1=316901&r2=316902&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Mon Oct 30 06:51:56 2017
@@ -43,6 +43,9 @@
define void @test_fadd_s32() #0 { ret void }
define void @test_fadd_s64() #0 { ret void }
+ define void @test_fsub_s32() #0 { ret void }
+ define void @test_fsub_s64() #0 { ret void }
+
define void @test_soft_fp_s64() #0 { ret void }
attributes #0 = { "target-features"="+vfp2"}
@@ -775,6 +778,58 @@ body: |
%d0 = COPY %2(s64)
BX_RET 14, _, implicit %d0
+...
+---
+name: test_fsub_s32
+# CHECK-LABEL: name: test_fsub_s32
+legalized: true
+regBankSelected: false
+selected: false
+# CHECK: registers:
+# CHECK: - { id: 0, class: fprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+# CHECK: - { id: 2, class: fprb, preferred-register: '' }
+
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %s0, %s1
+
+ %0(s32) = COPY %s0
+ %1(s32) = COPY %s1
+ %2(s32) = G_FSUB %0, %1
+ %s0 = COPY %2(s32)
+ BX_RET 14, _, implicit %s0
+
+...
+---
+name: test_fsub_s64
+# CHECK-LABEL: name: test_fsub_s64
+legalized: true
+regBankSelected: false
+selected: false
+# CHECK: registers:
+# CHECK: - { id: 0, class: fprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+# CHECK: - { id: 2, class: fprb, preferred-register: '' }
+
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %d0, %d1
+
+ %0(s64) = COPY %d0
+ %1(s64) = COPY %d1
+ %2(s64) = G_FSUB %0, %1
+ %d0 = COPY %2(s64)
+ BX_RET 14, _, implicit %d0
+
...
---
name: test_soft_fp_s64
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