[llvm] r316881 - [X86] Move some EVEX->VEX code to a helper function to prepare for a future patch. NFC

[Craig Topper via llvm-commits]

Author: ctopper
Date: Sun Oct 29 20:35:43 2017
New Revision: 316881

URL: http://llvm.org/viewvc/llvm-project?rev=316881&view=rev
Log:
[X86] Move some EVEX->VEX code to a helper function to prepare for a future patch. NFC

Modified:
    llvm/trunk/lib/Target/X86/X86EvexToVex.cpp

Modified: llvm/trunk/lib/Target/X86/X86EvexToVex.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86EvexToVex.cpp?rev=316881&r1=316880&r2=316881&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86EvexToVex.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86EvexToVex.cpp Sun Oct 29 20:35:43 2017
@@ -132,6 +132,38 @@ void EvexToVexInstPass::AddTableEntry(Ev
   EvexToVexTable[EvexOp] = VexOp;
 }
 
+static bool usesExtendedRegister(const MachineInstr &MI) {
+  auto isHiRegIdx = [](unsigned Reg) {
+    // Check for XMM register with indexes between 16 - 31.
+    if (Reg >= X86::XMM16 && Reg <= X86::XMM31)
+      return true;
+
+    // Check for YMM register with indexes between 16 - 31.
+    if (Reg >= X86::YMM16 && Reg <= X86::YMM31)
+      return true;
+
+    return false;
+  };
+
+  // Check that operands are not ZMM regs or
+  // XMM/YMM regs with hi indexes between 16 - 31.
+  for (const MachineOperand &MO : MI.explicit_operands()) {
+    if (!MO.isReg())
+      continue;
+
+    unsigned Reg = MO.getReg();
+
+    assert(!(Reg >= X86::ZMM0 && Reg <= X86::ZMM31) &&
+           "ZMM instructions should not be in the EVEX->VEX tables");
+
+    if (isHiRegIdx(Reg))
+      return true;
+  }
+
+  return false;
+}
+
+
 // For EVEX instructions that can be encoded using VEX encoding
 // replace them by the VEX encoding in order to reduce size.
 bool EvexToVexInstPass::CompressEvexToVexImpl(MachineInstr &MI) const {
@@ -188,31 +220,8 @@ bool EvexToVexInstPass::CompressEvexToVe
   if (!NewOpc)
     return false;
 
-  auto isHiRegIdx = [](unsigned Reg) {
-    // Check for XMM register with indexes between 16 - 31.
-    if (Reg >= X86::XMM16 && Reg <= X86::XMM31)
-      return true;
-
-    // Check for YMM register with indexes between 16 - 31.
-    if (Reg >= X86::YMM16 && Reg <= X86::YMM31)
-      return true;
-
+  if (usesExtendedRegister(MI))
     return false;
-  };
-
-  // Check that operands are not ZMM regs or
-  // XMM/YMM regs with hi indexes between 16 - 31.
-  for (const MachineOperand &MO : MI.explicit_operands()) {
-    if (!MO.isReg())
-      continue;
-
-    unsigned Reg = MO.getReg();
-
-    assert (!(Reg >= X86::ZMM0 && Reg <= X86::ZMM31));
-
-    if (isHiRegIdx(Reg))
-      return false;
-  }
 
   const MCInstrDesc &MCID = TII->get(NewOpc);
   MI.setDesc(MCID);