[PATCH] D39108: [DAGCombine] Don't combine sext with extload if sextload is not supported and extload has multi users
Guozhi Wei via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 27 11:30:16 PDT 2017
Carrot updated this revision to Diff 120662.
Carrot marked 2 inline comments as done.
https://reviews.llvm.org/D39108
Files:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
test/CodeGen/PowerPC/selectiondag-sextload.ll
Index: test/CodeGen/PowerPC/selectiondag-sextload.ll
===================================================================
--- test/CodeGen/PowerPC/selectiondag-sextload.ll
+++ test/CodeGen/PowerPC/selectiondag-sextload.ll
@@ -0,0 +1,26 @@
+; RUN: llc --mtriple=powerpc64le-linux-gnu < %s | FileCheck %s
+
+; It tests in function DAGCombiner::visitSIGN_EXTEND_INREG
+; signext will not be combined with extload, and causes extra zext.
+
+declare void @g(i32 signext)
+
+define void @foo(i8* %p) {
+entry:
+ br label %while.body
+
+while.body:
+ %0 = load i8, i8* %p, align 1
+ %conv = zext i8 %0 to i32
+ %cmp = icmp sgt i8 %0, 0
+ br i1 %cmp, label %if.then, label %while.body
+; CHECK: lbz
+; CHECK: extsb.
+; CHECK-NOT: rlwinm
+; CHECK: ble
+
+if.then:
+ tail call void @g(i32 signext %conv)
+ br label %while.body
+}
+
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8274,10 +8274,14 @@
}
// fold (sext_inreg (extload x)) -> (sextload x)
+ // If sextload is not supported by target, we can only do the combine when
+ // load has one use. Doing otherwise can block folding the extload with other
+ // extends that the target does support.
if (ISD::isEXTLoad(N0.getNode()) &&
ISD::isUNINDEXEDLoad(N0.getNode()) &&
EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
- ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
+ ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile() &&
+ N0.hasOneUse()) ||
TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, EVT))) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
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