[PATCH] D39350: AMDGPU: Add CPUCoherentL2 feature

[Jan Vesely via Phabricator via llvm-commits]

jvesely added a comment.

In https://reviews.llvm.org/D39350#908697, @kzhuravl wrote:

> Is it going to be used with amdhsa os? Where can I find the spec for this?


I planned to use this to enable system level atomics that work between CPU and dGPU. atm it only works on kaveri/carrizo.

In https://reviews.llvm.org/D39350#908854, @t-tye wrote:

> Are we sure using SLC is the way to achieve this? IIRC SLC can be used for streaming, but does not ensure L2 bypass. On an APU the MTYPE=CC specifies the memory policy that support coherence.


The CI and GCN3 ISA specs for SLC say: "System Level Coherent. When set, accesses are forced to miss in level 2 texture cache and are coherent with system memory."
Has this been changed?
I only found MTYPE references to for image and buffer rsrc, is there a way to set it for flat ops?
The ISA specs also don't mention what values are allowed in those 3 bits.

In https://reviews.llvm.org/D39350#908959, @arsenm wrote:

> This seems like a property of an individual operation, not a subtarget


Why would that be? if I have a system scope atomic OP it needs SLC flag on dGPUs while it's OK on CC APUs.


Repository:
  rL LLVM

https://reviews.llvm.org/D39350