[PATCH] D39227: [X86][AVX] Update YMM version of instructions scheduling on btver2

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:550
+def WriteVBROADCASTY: SchedWriteRes<[JFPU01]> {
+  let Latency = 1;
+  let ResourceCycles = [2];
----------------
Default latency = 1 - so remove and just leave ResourceCycles?


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:589
+}
+def : InstRW<[WriteVMaskMovY], (instregex "VMASKMOVP(D|S)Yrm")>;
+
----------------
This is masked load, and we need 128 bit versions:
```
def WriteVMaskMovLd: SchedWriteRes<[JLAGU,JFPU01]> {
  let Latency = 6;
}
def : InstRW<[WriteVMaskMovLd], (instregex "VMASKMOVP(D|S)rm")>;

def WriteVMaskMovYLd: SchedWriteRes<[JLAGU,JFPU01]> {
  let Latency = 6;
  let ResourceCycles = [1,2];
}
def : InstRW<[WriteVMaskMovYLd], (instregex "VMASKMOVP(D|S)Yrm")>;
```


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:595
+}
+def : InstRW<[WriteVMaskMovYLd], (instregex "VMASKMOVP(D|S)Ymr")>;
+
----------------
This is masked store, and we need 128 bit versions:
```
def WriteVMaskMovSt: SchedWriteRes<[JFPU01,JSAGU]> {
  let Latency = 6;
}
def : InstRW<[WriteVMaskMovSt], (instregex "VMASKMOVP(D|S)mr")>;

def WriteVMaskMovYSt: SchedWriteRes<[JFPU01,JSAGU]> {
  let Latency = 6;
  let ResourceCycles = [2,1];
}
def : InstRW<[WriteVMaskMovYSt], (instregex "VMASKMOVP(D|S)Ymr")>;
```


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:604
+}
+def : InstRW<[WriteVMOVMSK], (instregex "VMOVMSKP(D|S)Yrr")>;
+
----------------
128-bit versions need fixing as well - they are Latency=3 too


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:612
+  let Latency = 4;
+  let ResourceCycles = [2, 2];
+}
----------------
Shouldn't this be [1,1]? (i.e. default - so remove?)


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:614
+}
+def : InstRW<[WriteVTESTY], (instregex "VTESTP(S|D)Yrr")>;
+
----------------
Add VPTESTYrr as well


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:618
+  let Latency = 9;
+  let ResourceCycles = [1, 4, 2];
+}
----------------
Where did you get [1, 4, 2] from ? Shouldn't this be [1,2,2]?


================
Comment at: lib/Target/X86/X86ScheduleBtVer2.td:620
+}
+def : InstRW<[WriteVTESTYLd], (instregex "VTESTP(S|D)Yrm")>;
+
----------------
VPTESTYrm as well


https://reviews.llvm.org/D39227