[PATCH] D39350: AMDGPU: Add CPUCoherentL2 feature

[Jan Vesely via Phabricator via llvm-commits]

jvesely created this revision.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl.

This will be used to generate SLC flag for atomics on dGPUs


Repository:
  rL LLVM

https://reviews.llvm.org/D39350

Files:
  lib/Target/AMDGPU/AMDGPU.td
  lib/Target/AMDGPU/AMDGPUSubtarget.cpp
  lib/Target/AMDGPU/AMDGPUSubtarget.h
  lib/Target/AMDGPU/Processors.td


Index: lib/Target/AMDGPU/Processors.td
===================================================================
--- lib/Target/AMDGPU/Processors.td
+++ lib/Target/AMDGPU/Processors.td
@@ -121,7 +121,7 @@
 >;
 
 def : ProcessorModel<"kaveri",     SIQuarterSpeedModel,
-  [FeatureISAVersion7_0_0]
+  [FeatureISAVersion7_0_0, FeatureCPUCoherentL2]
 >;
 
 def : ProcessorModel<"gfx701",     SIFullSpeedModel,
@@ -160,7 +160,7 @@
 >;
 
 def : ProcessorModel<"carrizo", SIQuarterSpeedModel,
-  [FeatureISAVersion8_0_1]
+  [FeatureISAVersion8_0_1, FeatureCPUCoherentL2]
 >;
 
 def : ProcessorModel<"fiji",    SIQuarterSpeedModel,
Index: lib/Target/AMDGPU/AMDGPUSubtarget.h
===================================================================
--- lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -171,6 +171,7 @@
   bool HasVertexCache;
   short TexVTXClauseSize;
   bool ScalarizeGlobal;
+  bool HasCPUCoherentL2;
 
   // Dummy feature to use for assembler in tablegen.
   bool FeatureDisable;
@@ -339,6 +340,10 @@
     return (getGeneration() >= EVERGREEN) && hasHWFP64();
   }
 
+  bool hasCPUCoherentL2() const {
+   return HasCPUCoherentL2;
+  }
+
   TrapHandlerAbi getTrapHandlerAbi() const {
     return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone;
   }
Index: lib/Target/AMDGPU/AMDGPUSubtarget.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+++ lib/Target/AMDGPU/AMDGPUSubtarget.cpp
@@ -150,6 +150,7 @@
     HasSDWAMac(false),
     HasSDWAOutModsVOPC(false),
     HasDPP(false),
+    HasCPUCoherentL2(false),
     FlatAddressSpace(false),
     FlatInstOffsets(false),
     FlatGlobalInsts(false),
Index: lib/Target/AMDGPU/AMDGPU.td
===================================================================
--- lib/Target/AMDGPU/AMDGPU.td
+++ lib/Target/AMDGPU/AMDGPU.td
@@ -286,6 +286,12 @@
   "Support clamp for integer destination"
 >;
 
+def FeatureCPUCoherentL2 : SubtargetFeature<"cpu-coherent-l2",
+  "HasCPUCoherentL2",
+  "true",
+  "GPU L2 cache can be configured to be CPU coherent in HSA mode"
+>;
+
 //===------------------------------------------------------------===//
 // Subtarget Features (options and debugging)
 //===------------------------------------------------------------===//


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